View AK4955_4600935.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

[AK4955] ms1343-e-00 2011/12 - 1 - general description the AK4955 is a 24bit stereo codec with a microphone am plifier, speaker amplif ier, video amplifier, ldo, and dsp. the input circuits include a microphone amplifier and the output circuits include a speaker amplifier. it is suitable for port able application with recording/play back function. a one channel composite in/out video amplifier is also integrated. t he internal charge pump generates a negative power eliminating the need for ac-coupling capacitors. the AK4955 is availabl e in a small 36pin csp (3.0mm x 3.1mm, 0.5mm pitch), savi ng mounting area on the board. features 1. recording functions ? stereo single-ended input with two selectors ? mic amplifier (+24db/+21db/+18db/ +16db/+14db/+11db/+8db/+5db/0db) ? digital alc (automatic level control) (setting range: +36db ? 54db, 0.375db step) ? adc performance: s/(n+d): 81db, dr, s/n: 88db (mic-amp=+18db) s/(n+d): 82db, dr, s/n: 96db (mic-amp=0db) ? microphone sensitivity compensation ? 5 band notch filter ? stereo separation emphasis circuit ? digital mic interface 2. playback functions ? digital de-emphasis filter (tc= 50/15s, fs=32khz, 44.1khz, 48khz) ? soft mute ? digital alc (automatic level control) - setting range: +36db ~ ? 54db, 0.375db step ? digital volume control (+12db ~ ? 115db, 0.5db step & mute) ? stereo separation emphasis circuit ? stereo line output - output voltage: +2dbv(1.26vrms) (lvdd= 4.8v) 2.52vpp (lvdd=3.3v) - s/(n+d): 85db, s/n: 92db ? mono mixing output ? mono speaker-amplifier - s/(n+d): 70db@150m w, 60db@250mw, - s/n: 95db - btl output - output power: 600mw@8 (svdd=4.8v) 400mw@8 (svdd=3.3v) ? analog mixing: mono input ? beep generator AK4955 24bit stereo codec with mic/spk/ca p -less v ideo- a mp/ ldo & dsp
[AK4955] ms1343-e-00 2011/12 - 2 - 3. power management function ? thermal shut down 4. master clock: (1) pll mode ? frequencies: 11.2896mhz, 12mhz, 13. 5mhz, 24mhz, 27mhz (mcki pin) 32fs or 64fs (bick pin) (2) external clock mode ? frequencies: 256fs, 512fs or 1024fs (mcki pin) 5. output master clock frequency: 32fs/64fs/128fs/256fs 6. sampling frequencies ? pll slave mode (bick pin): 7.35khz ~ 48khz ? pll slave mode (mcki pin): 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? pll master mode: 8khz, 11.025khz, 12khz, 16khz, 22.05kh z, 24khz, 32khz, 44.1khz, 48khz ? ext master/slave mode: 7.35khz ~ 48khz (256fs), 7.35khz 48khz (512fs), 7.35khz 13khz (1024fs) 7. p i/f: 3-wire serial, i 2 c bus (ver 1.0, 400khz fast-mode) 8. master/slave mode 9. audio interface format: msb first, 2?s complement ? adc: 24bit msb justified, 16/24bit i 2 s ? dac: 24bit msb justified, 16bit lsb justified, 24bit lsb justified, 16/24bit i 2 s 10. video functions ? one composite signal input ? cap-less video amplifier for composite signal output gain: +6 / +9 / +12 / +16.5db ? low pass filter ? charge pump circuit for negative power supply 11. ta = ? 30 85 c 12. power supply: ? analog power supply (avdd): 2.7 ~ 3.6v ? digital power supply (dvdd): 1.6 ~ 2.0v ? line output power supply (lvdd): 2.7 ~ 5.5v ? speaker power supply (svdd): 2.7 ~ 5.5v ? digital i/o power supply (tvdd): dvdd-0.2 ~ 3.6v 13. package: 36pin csp (3.0 x 3.1mm, 0.5mm pitch)
[AK4955] ms1343-e-00 2011/12 - 3 - block diagram bick lrck sdto sdti pll pmpll mcko mcki vout pm v composite video out +6/9/12/16.5db lpf pmspk speaker spp spn spk-amp control register cclk/scl cdtio/cad0 csn/sda i2c mic-amp pm micl pmmicr mic power supply pmm p pdn audio i/f vin clamp clk gen pmcp stereo emphasis pm dac d/a dem mono/ stereo dvol smute internal mic external mic mpwr lin1 rin1 lin2 rin2 avdd a/d hpf pmadl or pmadr pmlo line out lout rout svdd charge pump pvee ( dsp block ) ldo: 2.3v analog logic tvdd vcom vss1 vss2 regfil dvdd mic power, video-out-amp vss3 lvdd pmpfil 1 ban d eq min pmbpe pmbpg beep gen lpf 4 band eq alc dsp2 pmdsp pmdsp dsp1 hpf3 eq0 figure 1. block diagram total: 36pin
[AK4955] ms1343-e-00 2011/12 - 4 - ordering guide AK4955ecb 30 a +85 q c 36pin csp (0.5mm pitch) black type akd4955 evaluation board for AK4955 pin layout a bc e d 6 5 3 4 1 2 top view f 6 mcki sdti rin1 lin1 svdd spn 5 bick lrck rout lvdd spp vss3 4 vss2 dvdd lout rin2 vss1 vcom 3 sdto tvdd min lin2 mpwr regfil 2 mcko cdtio /cad0 vout i2c avdd vss1 1 cclk /scl csn /sda pdn vin vss1 pvee a b c d e f top view
[AK4955] ms1343-e-00 2011/12 - 5 - pin/function no pin name i/o function power supply e2 avdd - analog power supply pin, 2.7 ~ 3.6v d5 lvdd lineout-amp power supply pin, 2.7 ~ 5.5v f4 vcom o common voltage output pin bias voltage of adc inputs and dac outputs. e1 e4 f2 vss1 - ground 1 pin b4 dvdd - digital power supply pin, 1.6 ~ 2.0v b3 tvdd - digital interface supply pin, dvdd-0.2 ~ 3.6v f3 regfil - ldo voltage output pin for analog logic (typ 2.3v) this pin must be connected to vss1 with 2.2 f 50% capacitor in series. a4 vss2 - ground 2 pin e6 svdd - speaker-amp power supply pin, 2.7 ~ 5.5v f5 vss3 - ground 3 pin f1 pvee o negative charge pump output pin connect to vss1 with a 2.2 p f capacitor which is low esr (equivalent series resistance) over all temperature range. audio interface a6 mcki i master clock input pin ( note 1 ) a2 mcko o master clock output pin b5 lrck i/o channel clock pin ( note 1 ) a5 bick i/o audio serial data clock pin ( note 1 ) b6 sdti i audio serial data input pin ( note 1 ) a3 sdto o audio serial data output pin control register interface csn i chip select pin (i2c pin = ?l?) ( note 1 ) b1 sda i/o control data input/output pin (i2c pin = ?h?) ( note 1 ) cclk i control data clock pin (i2c pin = ?l?) ( note 1 ) a1 scl i control data clock pin (i2c pin = ?h?) ( note 1 ) cdtio i/o control data input/output pin (i2c pin = ?l?) ( note 1 ) b2 cad0 i chip address select pin (i2c pin = ?h?) ( note 1 ) d2 i2c i control mode select pin ?h?: i 2 c bus, ?l?: 3-wire serial ( note 1 )
[AK4955] ms1343-e-00 2011/12 - 6 - no pin name i/o function mic block lin1 i lch analog input line input 1pin (dmic bit = ?0?) d6 dmdat i digital microphone data input pin (dmic bit = ?1?) ( note 1 ) rin1 i rch analog input 1 pin (dmic bit = ?0?) c6 dmclk o digital microphone clock pin (dmic bit = ?1?) d3 lin2 i lch analog input 2 pin d4 rin2 i rch analog input 2 pin e3 mpwr o mic power supply pin for microphone min block c3 min i mono analog signal input pin lineout block c4 lout o lch analog output pin c5 rout o rch analog output pin speaker block e5 spp o speaker amp positive output pin f6 spn o speaker amp negative output pin video block d1 vin i composite video input pin c2 vout o composite video output pin other functions c1 pdn i reset & power-down pin ( note 1 ) ?l?: reset & power-down, ?h?: normal operation note 1. all input pins except analog input pins (min, lin1, rin1, lin2, rin2, vin) must not be allowed to float. handling of unused pin unused i/o pins must be processed appropriately as below. classification pin name setting analog mpwr, spn, spp, lout, rout, min, rin2, lin2, lin1/dmdat, rin1/dmclk, vin, vout these pins must be open. mcko, sdto these pins must be open. mcki, sdti these pins must be connected to vss2. digital lrck, bick m/s bit = ?0?, these pins must be connected to vss2.
[AK4955] ms1343-e-00 2011/12 - 7 - absolute maximum ratings (vss1=vss2=vss3= 0v; note 2 ) parameter symbol min max unit power supplies: analog digital lineout-amp speaker-amp avdd dvdd lvdd svdd ? 0.3 ? 0.3 ? 0.3 ? 0.3 6.0 2.5 6.0 6.0 v v v v digital i/o tvdd ? 0.3 6.0 v input current, any pin except supplies iin - 10 ma analog input voltage ( note 4 ) vina ? 0.3 avdd+0.3 v ( note 5 ) vind ? 0.3 tvdd+0.3 v digital input voltage ( note 7 ) vind ? 0.3 6.0 v ambient temperature (powered applied) ta ? 30 85 c storage temperature tstg ? 65 150 c maximum power dissipation ( note 7 ) pd1 - 880 mw note 2. all voltages are with respect to ground. note 3. vss1, vss2 and vss3 must be connected to the same analog ground plane. note 4. min, lin1, rin1, lin2, rin2, vin pins note 5. pdn, cdtio/cad0, sdti, lrck, bick, mcki and i2c pins note 6. csn/sda and cclk/scl pins note 7. this power is the AK4955 internal dissipation that does not include power dissipation of externally connected speakers. the maximum junction temperature is 125 c and ja (junction to ambient) is 35 c/w at jesd51-9 (2p2s). when pd =880mw and the ja is 35 c/w, the junction temperature does not exceed 125 c. in this case, there is no case that the AK4955 is damaged by its internal power dissipation. therefore, the AK4955 should be used in the condition of ja ? 35 c/w. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (vss1=vss2=vss3= 0v; note 2 ) parameter symbol min typ max unit power supplies ( note 8 ) analog digital lineout-amp speaker-amp avdd dvdd lvdd svdd 2.7 1.6 2.7 2.7 3.3 1.8 3.3 3.3 3.6 2.0 5.5 5.5 v v v v digital i/o ( note 9 ) tvdd dvdd-0.2 or 1.6 1.8 3.6 v note 2. all voltages are with respect to ground. note 8. the power-up sequence between avdd, dvdd, tvdd, lvdd and svdd is not critical . the pdn pin must be ?l? upon power up, and should be changed to ?h? after all pow er supplies are supplied to avoid an internal circuit error. note 9. the minimum value is higher voltage between (dvdd-0.2)v and 1.6v. * when tvdd is powered on and the pdn pi n is ?l?, avdd dvdd, lvdd and svdd can be powered on/off. when the AK4955 is powered on from power-down state, the pdn pin must be ?h? after all power supplies (avdd, dvdd, tvdd, lvdd and svdd) are on. * akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4955] ms1343-e-00 2011/12 - 8 - analog characteristics (ta=25 c; avdd=lvdd=svdd=3.3v, dvdd=tvdd= 1.8v; vss1 =vss2=vss3= 0v; fs=48khz, bick=64fs; signal frequency=1khz; 24bit data; measurement bandwidth=20hz 20khz; unless otherwise specified) parameter min typ max unit mic amplifier: lin1, rin1, lin2, rin2 pins input resistance 23 33 43 k mgain3-0 bits = ?0000? -1 0 +1 db gain mgain3-0 bits = ?0001? +4 +5 +6 db mgain3-0 bits = ?0010? +7 +8 +9 db mgain3-0 bits = ?0011? +10 +11 +12 db mgain3-0 bits = ?0100? +13 +14 +15 db mgain3-0 bits = ?0101? +15 +16 +17 db mgain3-0 bits = ?0110? +17 +18 +19 db mgain3-0 bits = ?0111? +20 +21 +22 db mgain3-0 bits = ?1000? +23 +24 +25 db mic power supply: mpwr pin micl bit = ?0? 2.3 2.5 2.7 v output voltage micl bit = ?1? 2.0 2.2 2.4 v output noise level (a-weighted) - ? 108 - dbv load resistance 0.5 - - k load capacitance - - 30 pf psrr (fin = 1khz) - 100 - db adc analog input characteristics : lin1/rin1/lin2/rin2 pins adc (programmable filter = dsp=off) resolution - - 24 bits ( note 12 ) - 0.261 - vpp input voltage ( note 11 ) ( note 13 ) 1.86 2.07 2.28 vpp ( note 12 ) 71 81 - dbfs s/(n+d) ( ? 1dbfs) ( note 13 ) - 82 - dbfs ( note 12 ) 78 88 - db d-range ( ? 60dbfs, a-weighted) ( note 13 ) - 96 - db ( note 12 ) 78 88 - db s/n (a-weighted) ( note 13 ) - 96 - db ( note 12 ) 75 90 - db interchannel isolation ( note 13 ) - 100 - db ( note 12 ) - 0 0.5 db interchannel gain mismatch ( note 13 ) - 0 0.5 db note 10. micl bit must be set to ?1? when avdd=2.7 ~ 3.6v, and it must be set to ?0? when avdd=2.9 ~ 3.6v. note 11. vin = 0.9 x 2.3vpp (typ) @mgain3-0 bits = ?0000? (0db) note 12. mgain3-0 bits = ?0110? (+18db) note 13. mgain3-0 bits = ?0000? (0db)
[AK4955] ms1343-e-00 2011/12 - 9 - parameter min typ max unit dac characteristics: resolution - - 24 bits stereo line output characteristics: dac lout, rout pins, alc= off, dvol=ovol =0db, r l =10k , pmbp bit = ?0?, lvcm1-0 bits = ?00? lvcm1-0 bits = ?00? ( note 14 ) 1.94 2.16 2.38 vpp lvcm1-0 bits = ?01? ( note 15 ) 2.27 2.52 2.77 vpp lvcm1-0 bits = ?10? ( note 16 ) 3.02 3.36 3.70 vpp output voltage lvcm1-0 bits = ?11?( note 17 ) 3.40 3.78 4.16 vpp s/(n+d) ( ? 3dbfs) ( note 14 , note 15 ) 75 85 - db s/n (a-weighted) 82 92 - db interchannel isolation 85 100 - db interchannel gain mismatch - 0 0.8 db load resistance 10 - - k load capacitance - - 30 pf psrr (fin = 1khz) - 80 - db speaker-amp characteristics: dac spp/spn pins, alc=o ff, dvol=ovol =0db, r l =8 , btl output voltage spkg1-0 bits = ?00?, ? 0.5dbfs (po=150mw) - 3.18 - vpp spkg1-0 bits = ?01?, ? 0.5dbfs (po=250mw) 3.20 4.00 4.80 vpp spkg1-0 bits = ?10?, ? 0.5dbfs (po=400mw) - 1.79 - vrms spkg1-0 bits = ?11? ? 0.5dbfs (po=600mw, svdd = 4.8v) - 2.19 - vrms s/(n+d) spkg1-0 bits = ?00?, ? 0.5dbfs (po=150mw) - 70 - db spkg1-0 bits = ?01?, ? 0.5dbfs (po=250mw) 20 60 - db spkg1-0 bits = ?10?, ? 0.5dbfs (po=400mw) - 20 - db spkg1-0 bits = ?11? ? 0.5dbfs (po=600mw, svdd = 4.8v) - 20 - db s/n spkg1-0 bits = ?01?, ? 0.5dbfs (po=250mw) (a-weighted) 85 95 - db load resistance 6.8 - - load capacitance - - 30 pf psrr (fin = 1khz) - 60 - db note 14. lvdd must be in the range of 2.7v~5.5v when lvcm1-0 bits = ?00?. the common voltage is typ. 1.30v. note 15. lvdd must be in the range of 3.0v~5.5v when lvcm1-0 bits = ?01?. the common voltage is typ. 1.42v. note 16. lvdd must be in the range of 4.0v~5.5v when lvcm1-0 bits = ?10?. the common voltage is typ. 1.92v. note 17. lvdd must be in the range of 4.5v~5.5v when lvcm1-0 bits = ?11?. the common voltage is typ. 2.10v.
[AK4955] ms1343-e-00 2011/12 - 10 - parameter min typ max unit mono input: min pin, external resistance mode (pmbp bit =?1?, bpm1-0 bits = ?01?, bpvcm bit = ?0?, bplvl3-0 bits = ?0000?), external input resistance= 72k maximum input voltage ( note 18 ) - - 1.54 vpp gain ( note 19 ) lvcm1-0 bits = ?00? - ? 1.34 - db lvcm1-0 bits = ?01? ? 4.5 0 +4.5 db lvcm1-0 bits = ?10? - +2.50 - db min ? lout lvcm1-0 bits = ?11? - +3.52 - db min ? spp/spn alc bit = ?0?, spkg1-0 bits = ?00? +1.6 +6.1 +10.6 db alc bit = ?0?, spkg1-0 bits = ?01? - +8.1 - db alc bit = ?0?, spkg1-0 bits = ?10? - +10.1 - db alc bit = ?0?, spkg1-0 bits = ?11? - +12.1 - db alc bit = ?1?, spkg1-0 bits = ?00? - +8.1 - db alc bit = ?1?, spkg1-0 bits = ?01? - +10.1 - db alc bit = ?1?, spkg1-0 bits = ?10? - +12.1 - db alc bit = ?1?, spkg1-0 bits = ?11? - +14.1 - db mono input: min pin, internal resistance mode (pmbp bit =?1?, bpm1-0 bits = ?00?, bpvcm bit = ?0?, bplvl3-0 bits = ?0000?) input resistance 50 72 94 k maximum input voltage ( note 18 ) - - 1.54 vpp gain lvcm1-0 bits = ?00? - ? 1.34 - db min ? lout lvcm1-0 bits = ?01? ? 1.0 0 +1.0 db lvcm1-0 bits = ?10? - +2.50 - db lvcm1-0 bits = ?11? - +3.52 - db min ? spp/spn alc bit = ?0?, spkg1-0 bits = ?00? +4.1 +6.1 +8.1 db alc bit = ?0?, spkg1-0 bits = ?01? - +8.1 - db alc bit = ?0?, spkg1-0 bits = ?10? - +10.1 - db alc bit = ?0?, spkg1-0 bits = ?11? - +12.1 - db alc bit = ?1?, spkg1-0 bits = ?00? - +8.1 - db alc bit = ?1?, spkg1-0 bits = ?01? - +10.1 - db alc bit = ?1?, spkg1-0 bits = ?10? - +12.1 - db alc bit = ?1?, spkg1-0 bits = ?11? - +14.1 - db note 18. the maximum value is avdd vpp when bpvcm bit = ?1?. however, it must be set as the amplitude after min-amp is less than 0.1vpp. (set by bplvl3-0 bits) note 19. the gain is in inverse proportion to external input resistance.
[AK4955] ms1343-e-00 2011/12 - 11 - parameter min typ max unit video signal input external resistor ( note 21 ) r1 ( figure 2 ) - - 600 external capacitor c1 ( figure 2 ) 0.05 0.1 0.2 f maximum input voltage: vg1-0 bits = ?00? (+6db) - 1.0 1.24 vpp pull down current - 0.5 - a video analog output ( figure 3 ) vg1-0 bits = ?00?, 1.0vpp input 5.5 6.0 6.5 vg1-0 bits = ?01?, 0.7vpp input 8.5 9.0 9.5 vg1-0 bits = ?10?, 0.5vpp input 11.5 12.0 12.5 output gain fin =100khz sine wave input ( note 20 ) vg1-0 bits = ?11?, 0.3vpp input 16 16.5 17 db signal input (pedestal level) ? 100 0 100 mv dc output offset level ( note 20 ) no signal input - ? 572 - mv s/n ( note 22 ) vg1-0 bits = ?00?(+6db) bw = 100kh 6mhz, s = 0.7vpp input 60 70 - db maximum output voltage ( note 20 ) fin =100khz (sine wave) 2.62 - - vpp secondary harmonic distortion vg1-0 bits = ?00?(+6db), fin = 3.58mhz, 1.0vpp: ? 40 ~ 100ire, sine wave input - ? 40 ? 30 db load resistance 140 150 - load capacitance c2 ( figure 3 ) c3 ( figure 3 ) - - - - 15 400 pf pf fin = 10khz - 58 - db psrr vg1-0 bits = ?00?(+6db) fin = 100khz - 53 - db lpf for vin signal : ( note 20 ) frequency response (fin = 100khz, 1.0vpp, sine wave input) response at 6.75mhz ? 3.0 ? 0.5 +2.0 response at 27mhz - ? 40 ? 20 db group delay |gd3mhz ? gd6mhz| - 15 100 ns note 20. this is a value at measurement point in figure 3 . 1.0vpp input is the value when vg1-0 bits =?00?. input amplitude is in inverse proportion to the gain. s/n is measured at measuring point 2. note 21. pmv bit must be set to ?0? if the input impedance of the vin pin exceeds 600 ? in case of the input signal is stopped or the input circuit of the vin pin is powered down. note 22. s/n = 20xlog (output voltage[vpp]/noise level[vrms]). output voltage = 0.7 [vpp]. AK4955 vin pin r1 from video dac c1 figure 2. external resistor of video signal input pin video signal output 75 ohm 75 ohm c3 r2 r3 c2 measurement point1 measurement point2 figure 3. load capacitance c2 and c3
[AK4955] ms1343-e-00 2011/12 - 12 - parameter min typ max unit power supplies: power up (pdn pin = ?h?) all circuit power-up ( note 23 ) avdd - 13.8 21 ma lvdd + svdd - 1.3 2.0 ma dvdd + tvdd - 7.1 10.7 ma mic + adc ( note 24 ) avdd - 2.9 - ma dvdd +tvdd - 1.3 - ma dac + lineout ( note 25 ) avdd - 1.7 - ma lvdd 0.3 dvdd +tvdd - 1.0 - ma dac + spk-amp ( note 26 ) avdd - 1.5 - ma svdd 1.0 dvdd +tvdd - 1.0 - ma video block ( note 27 ) avdd - 10.5 - ma power down (pdn pin = ?l?) ( note 28 ) all vdd - 1 5 a note 23. pmadl=pmadr=pmdac=pmpfil=pm dsp=pmlo=pmspk=pmpll=mcko=pmbp=pmmp =pmmicr =pmmicl =m/s =pmv =pmcp bits = ?1?, spk-amp no load, black signal is input to the vin pin. in this case, the output current of the mpwr pin is 0ma. the sampling frequency is 48khz. 1khz signal with 1.845vpp amplitude is input to lin and 1.2khz signal with 1.845vpp amplitude is input to rin while the data path setting is dspbp=pfdac=adcdo bits = ?1?. noise canceling program is run by the dsp. note 24. in ext slave mode (pmpll=m/s=mcko bits =?0?), pmadl = pmadr = pmmicl = pmmiclr bits = ?1?, and pmdsp bit = ?0?. note 25. in ext slave mode (pmpll=m/s=mcko bits =?0? ), pmdac = pmlo bits= ?1?, and pmdsp bit = ?0?. note 26. in ext slave mode (pmpll=m/s=mcko bits =?0? ), pmdac = pmspk =sppsn bits = ?1?, and pmdsp bit =?0? with no load at the spk-amp. note 27. pmv =pmcp bits = ?1?, no load, and the black signal is only input to the vin pin. note 28. all digital input pins are fixed to tvdd or vss2.
[AK4955] ms1343-e-00 2011/12 - 13 - filter characteristics (ta =25 c; avdd=2.7 3.6v, dvdd = 1.6 ~ 2.0v, lvdd = 2.7 ~ 5.5v, svdd= 2.7 ~ 5.5v, tvdd = dvdd-0.2 3.6v; fs=48khz, dem= off) parameter symbol min typ max unit adc digital filter (decimation lpf): passband ( note 29 ) 0.16db pb 0 - 18.8 khz ? 0.66db - 21.1 - khz ? 1.1db - 21.7 - khz ? 6.9db - 24.1 - khz stopband ( note 29 ) sb 28.4 - - khz passband ripple pr - - 0.16 db stopband attenuation sa 73 - - db group delay ( note 30 ) gd - 16 - 1/fs group delay distortion gd - 0 - s adc digital filter (hpf): hpfc1-0 bits = ?00? frequency response ? 3.0db fr - 3.7 - hz ( note 29 ) ? 0.5db - 10.9 - hz ? 0.1db - 23.9 - hz dac digital filter (lpf): passband ( note 29 ) 0.05db pb 0 - 21.8 khz ? 6.0db - 24 - khz stopband ( note 29 ) sb 26.2 - - khz passband ripple pr - - 0.05 db stopband attenuation sa 54 - - db group delay ( note 30 ) gd - 22 - 1/fs dac digital filter (lpf) + scf: frequency response: 0 20.0khz fr - 1.0 - db note 29. the passband and stopband frequencies scale with fs (s ystem sampling rate). each response refers to that of 1khz. for example, it is 0.454 x fs (adc) when pb=21.7khz (@ ? 1.1db). note 30. a calculating delay time which is induced by digital filtering. this time is from the input of an analog signal to the setting of 24-bit data of both channels to the adc output register. for the dac, this time is from setting the 24-bit data of a channel from the input register to the output of analog signal. for the signal through the block controlled by pmpfil bit, the group delay is increased by 4/fs (typ) at adc block, by 7/fs (typ) at dac block from the value above in both recording and playback modes if there is no pha se change by the iir filter. the group delay is increased more for the signal through the block controlled by pmdsp bit.
[AK4955] ms1343-e-00 2011/12 - 14 - dc characteristics (ta =25 c; avdd = 2.7 ~ 3.6v, dvdd = 1.6 ~ 2.0v, lvdd = 2.7 ~ 5.5v, svdd= 2.7 ~ 5.5v, tvdd =dvdd-0.2 3.6v; fs= 48khz; dem=off) parameter symbol min typ max unit audio interface & serial p interface (cdtio/cad0, csn/sda, cclk/scl, i2c, pdn, bick, lrck, sdti, mcki pins ) high-level input voltage (tvdd 2.2v) (tvdd < 2.2v) low-level input voltage (tvdd 2.2v) (tvdd < 2.2v) vih vih vil vil 70%tvdd 80%tvdd - - - - - - - - 30%tvdd 20%tvdd v v v v audio interface & serial p interface (cdtio , sda mcko, bick, lrck, sdto pins output) high-level output voltage (iout = ? 80 a) low-level output voltage (except sda pin : iout = 80 a) (sda pin, 2.0v tvdd 3.6v: iout = 3ma) (sda pin, 1.6v tvdd < 2.0v: iout = 3ma) voh vol1 vol2 vol2 tvdd ? 0.2 - - - - - - - - 0.2 0.4 20%tvdd v v v v input leakage current iin1 - - 10 a digital mic interface (dmdat pin input ; dmic bit = ?1?) high-level input voltage low-level input voltage vih2 vil2 65%avdd - - - - 35%avdd v v input leakage current iin2 - - 10 a digital mic interface (dmclk pin output ; dmic bit = ?1?) high-level output voltage (iout= ? 80 a) low-level output voltage (iout= 80 a) voh3 vol3 avdd-0.4 - - - - 0.4 v v
[AK4955] ms1343-e-00 2011/12 - 15 - switching characteristics (ta =25 c; avdd = 2.7 ~ 3.6v, dvdd = 1.6 ~ 2.0v, lvdd=2.7~5.5v, svdd = 2.7~5.5v, tvdd = dvdd-0.2 3.6v; c l =20pf) parameter symbol min typ max unit pll master mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.256 - 12.288 duty cycle dmck 40 50 60 mhz % lrck output timing frequency fs 8 - 48 khz duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % pll slave mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.256 - 12.288 mhz duty cycle dmck 40 50 60 % lrck input timing frequency fs 8 - 48 khz duty duty 45 - 55 % bick input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns
[AK4955] ms1343-e-00 2011/12 - 16 - parameter symbol min typ max unit pll slave mode (pll reference clock = bick pin) lrck input timing frequency fs 7.35 - 48 khz duty duty 45 - 55 % bick input timing period pll3-0 bits = ?0010? tbck - 1/(32fs) - ns pll3-0 bits = ?0011? tbck - 1/(64fs) - ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns external slave mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 24.576 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck input timing frequency 256fs fs 7.35 - 48 khz 512fs fs 7.35 - 48 khz 1024fs fs 7.35 - 13 khz duty duty 45 - 55 % bick input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns external master mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 24.576 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck output timing frequency fs 7.35 - 48 khz duty cycle duty - 50 - % bick output timing period bcko bit = ?0? tbck - 1/(32fs) - ns bcko bit = ?1? tbck - 1/(64fs) - ns duty cycle dbck - 50 - %
[AK4955] ms1343-e-00 2011/12 - 17 - parameter symbol min typ max unit audio interface timing master mode bick ? ? to lrck edge ( note 31 ) tmblr ? 40 - 40 ns lrck edge to sdto (msb) (except i 2 s mode) tlrd ? 70 - 70 ns bick ? ? to sdto tbsd ? 70 - 70 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns slave mode lrck edge to bick ? ? ( note 31 ) tlrb 50 - - ns bick ? ? to lrck edge ( note 31 ) tblr 50 - - ns lrck edge to sdto (msb) (except i 2 s mode) tlrd - - 80 ns bick ? ? to sdto tbsd - - 80 ns sdti hold time tsdh 50 - - ns sdti setup time tsds 50 - - ns control interface timing (3-wire mode) ( note 32 ) cclk period tcck 80 - - ns cclk pulse width low tcckl 32 - - ns pulse width high tcckh 32 - - ns cdtio setup time tcds 16 - - ns cdtio hold time tcdh 16 - - ns csn ?h? time tcsw 60 - - ns csn edge to cclk ? ? ( note 33 ) tcss 20 - - ns cclk ? ? to csn edge ( note 33 ) tcsh 20 - - ns cclk ? ? to cdtio (at read command) tdcd - - 70 ns csn ? ? to cdtio (hi-z) (at read command)( note 35 ) tccz - - 70 ns control interface timing (i 2 c bus mode): scl clock frequency fscl - - 400 khz bus free time between transmissions tbuf 1.3 - - s start condition hold time (prior to first clock pulse) thd:sta 0.6 - - s clock low time tlow 1.3 - - s clock high time thigh 0.6 - - s setup time for repeated start condition tsu:sta 0.6 - - s sda hold time from scl falling ( note 36 ) thd:dat 0 - - s sda setup time from scl rising tsu:dat 0.1 - - s rise time of both sda and scl lines tr - - 0.3 s fall time of both sda and scl lines tf - - 0.3 s setup time for stop condition tsu:sto 0.6 - - s capacitive load on bus cb - - 400 pf pulse width of spike noise suppre ssed by input filter tsp 0 - 50 ns note 31. bick rising edge must not occur at the same time as lrck edge. note 32. when accessing to codec registers, the maximu m frequency of cclk for write operation is 12.5mhz and 6.75mhz for read operation, regardle ss of the operating frequency of the in ternal dsp. when accessing to the dsp, cclk and cdti interface timings are changed depe nding on the operating frequency of the internal dsp. for example, the dsp operating frequency (256times of the sampling frequency) is 12.288mhz, cclk and cdti timings are multiplied by 12.5/12.288. (except td cd and tccz) then, the maximum frequency of cclk is 12.288mhz. (when dsp ope rating frequency = 12.288mhz) note 33. cclk rising edge must not occur at the same time as csn edge. note 34. i 2 c-bus is a trademark of nxp b.v. note 35. it is the time of 10% potential change of the cdtio pin when r l =1k (pull-up to tvdd). note 36. data must be held for sufficient tim e to bridge the 300 ns transition time of scl.
[AK4955] ms1343-e-00 2011/12 - 18 - parameter symbol min typ max unit digital audio interface timing; c l =100pf dmclk output timing period tsck - 1/(64fs) - ns rising time tsrise - - 10 ns falling time tsfall - - 10 ns duty cycle dsck 40 50 60 % audio interface timing dmdat setup time tdsds 50 - - ns dmdat hold time tdsdh 0 - - ns power-down & reset timing pdn accept pulse width ( note 37 ) tapd 180 - - ns pdn reject pulse width ( note 37 ) trpd - - 50 ns pmadl or pmadr ? ? to sdto valid ( note 38 ) adrst1-0 bits =?00? tpdv - 1059 - 1/fs adrst1-0 bits =?01? adrst1-0 bits =?10? adrst1-0 bits =?11? tpdv tpdv tpdv - - - 267 531 135 - - - 1/fs 1/fs 1/fs note 37. the AK4955 can be reset by the pdn pin = ?l?. the pdn pin must held ?l? for more than 180ns for a certain reset. the AK4955 is not reset by the ?l? pulse less than 50ns. note 38. this is the count of lrck ? ? from the pmadl or pmadr bit = ?1?.
[AK4955] ms1343-e-00 2011/12 - 19 - timing diagram lrck 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckl 50%tvdd 1/fs tlrckh tlrckl 50%tvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 dmck = tmckl x fmck x 100 note 39. mcko is not available at ext master mode. figure 4. clock timing (pll/ext master mode) lrck 50%tvdd bick 50%tvdd sdto 50%tvdd tbsd tsds sdti vil tsdh vih tblr tbckl tdlr figure 5. audio interface ti ming (pll/ext master mode)
[AK4955] ms1343-e-00 2011/12 - 20 - 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl fmck mcko tmckl 50%tvdd dmck = tmckl x fmck x 100 duty = tlrckh x fs x 100 = tlrckl x fs x 100 figure 6. clock timing (pll slave mode; pll reference clock = mcki pin) 1/fclk mcki tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 7. clock timing (ext slave mode)
[AK4955] ms1343-e-00 2011/12 - 21 - lrck vih vil tblr bick vih vil tlrd sdto 50%tvdd tlrb tbsd tsds sdti vil tsdh vih msb figure 8. audio interface timing (pll/ext slave mode) csn vih vil tcss cclk tcds vih vil cdtio vih tcckh tcckl tcdh vil r/w a6 a5 tcck tcsh figure 9. write command input timing
[AK4955] ms1343-e-00 2011/12 - 22 - csn vih vil tcsh cclk vih vil cdtio vih tcsw vil d1 d0 d2 tcss figure 10. write data input timing csn cclk 50% tvdd cdtio vih d3 d2 d1 d0 tccz tdcd vil vih vil hi-z clock, h or l figure 11. read data output timing
[AK4955] ms1343-e-00 2011/12 - 23 - stop start start stop thigh thd:dat sda scl tbuf tlow tr tf tsu:dat vih vil thd:sta tsu:sta vih vil tsu:sto tsp figure 12. i 2 c bus mode timing tsck 65%avdd dmclk 35%avdd tsckl 50%avdd dsck = 100 x tsckl / tsck tsrise tsfall figure 13. dmclk clock timing dmclk 65%avdd dmdat tsds vih2 vil2 tsdh 35%avdd figure 14. audio interface timing (dclkp bit = ?1?) figure 15. audio interface timing (dclkp bit = ?0?) dmclk 65%avdd dmdat tsds vih2 vil2 tsdh 35%avdd
[AK4955] ms1343-e-00 2011/12 - 24 - pmadl bit or pmadr bit tpdv sdto 50%tvdd figure 16. power down & reset timing 1 tapd pdn vil trpd figure 17. power down & reset timing 2
[AK4955] ms1343-e-00 2011/12 - 25 - operation overview system clock there are the following five clock modes to interface with external devices ( table 1 , table 2 ). mode pmpll bit m/s bit pll3-0 bits figure pll master mode ( note 40 ) 1 1 table 4 figure 18 pll slave mode 1 (pll reference clock: mcki pin) 1 0 table 4 figure 19 pll slave mode 2 (pll reference clock: bick pin) 1 0 table 4 figure 20 ext slave mode 0 0 x figure 21 ext master mode 0 1 x figure 22 note 40. if m/s bit = ?1?, pmpll bit = ?0? and mcko bit = ?1? during the setting of pll master mode, the invalid clocks are output from mcko, bick and lrck pins . table 1. clock mode setting (x: don?t care) mode mcko bit mcko pin mcki pin bick pin lrck pin 0 l pll master mode 1 selected by ps1-0 bits selected by pll3-0 bits output (selected by bcko bit) output (1fs) 0 l pll slave mode (pll reference clock: mcki pin) 1 selected by ps1-0 bits selected by pll3-0 bits input ( 32fs) input (1fs) pll slave mode (pll reference clock: bick pin) 0 l gnd input ( 32fs) input (1fs) ext slave mode 0 l selected by fs3-0 bits input ( 32fs) input (1fs) ext master mode 0 l selected by fs1-0 bits output (selected by bcko bit) output (1fs) note 41. when m/s bit = ?1? and mcki is input, lrck and bick are output even if pmdac=pmadl= pmadr bits = ?0?. table 2. clock pins state in clock mode master mode/slave mode the m/s bit selects either master or sl ave mode. m/s bit = ?1? selects master m ode and ?0? selects slave mode. when the AK4955 is in power-down mode (pdn pin = ?l?) and when exits reset state, the AK4955 is in slave mode. after exiting reset state, the AK4955 goes to master mode by changing m/s bit to ?1?. when the AK4955 is in master mode, the lrck and bick pins are a floating state until m/s bit becomes ?1?. the lrck and bick pins of the AK4955 must be pulled-down or pulled-up by a resistor (about 100k ) externally to avoid the floating state. m/s bit mode 0 slave mode (default) 1 master mode table 3. select master/slave mode
[AK4955] ms1343-e-00 2011/12 - 26 - pll mode when pmpll bit is ?1?, a fully integrated analog phase locked loop (pll) circuit generates a clock that is selected by pll3-0 and fs3-0 bits. the pll lock times, when the ak 4955 is supplied stable clocks after pll is powered-up (pmpll bit = ?0? ?1?) or the sampling frequency is changed, are shown in table 4 . 1) pll mode setting mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency pll lock time (max) 2 0 0 1 0 bick pin 32fs 2 ms 3 0 0 1 1 bick pin 64fs 2 ms 4 0 1 0 0 mcki pin 11.2896mhz 10 ms 6 0 1 1 0 mcki pin 12mhz 10 ms 7 0 1 1 1 mcki pin 24mhz 10 ms 12 1 1 0 0 mcki pin 13.5mhz 10 ms (default) 13 1 1 0 1 mcki pin 27mhz 10 ms others others n/a table 4. pll mode setting (*fs: sampling frequency, n/a: not available) 2) setting of sampling frequency in pll mode when pll2 bit is ?1? (pll reference clock input is mcki pin), the sampling frequency is selected by fs3-0 bits as defined in table 5 . mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz (default) 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 5 0 1 0 1 11.025khz 7 0 1 1 1 22.05khz 10 1 0 1 0 32khz 11 1 0 1 1 48khz 15 1 1 1 1 44.1khz others others n/a table 5. setting of sampling frequency at pll2 bit = ?1? and pmpll bit = ?1? (reference clock = mcki pi n), (n/a: not available) when pll2 bit is ?0? (pll reference clock input pin is the bick pin), the sampling frequency is selected by fs3-2 bits. ( table 6 ). mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 0 x x 7.35khz d fs d 12khz (default) 1 0 1 x x 12khz < fs d 24khz 2 1 0 x x 24khz < fs d 48khz others others n/a table 6. setting of sampling frequency at pll2 bit = ?0? and pmpll bit = ?1? pll slave mode 2 (pll reference clock: bick pin), (x: don?t care, n/a: not available)
[AK4955] ms1343-e-00 2011/12 - 27 - pll unlock state 1) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in this mode, lrck and bick pins go to ?l?, and irre gular frequency clock is output from the mcko pin when mcko bit is ?1? before the pll goes to lock state after pmpll bit = ?0? ?1?. if mcko bit is ?0?, the mcko pin outputs ?l? ( table 7 ). after the pll is locked, a first period of lrck and bick may be invalid clock, but these clocks return to normal state after a period of 1/fs. the bick and lrck pins do not output irregular frequency cl ocks such as pll unlock state by setting pmpll bit to ?0?. during pmpll bit = ?0?, these pins output the same clocks as ext master mode. mcko pin pll state mcko bit = ?0? mcko bit = ?1? bick pin lrck pin after pmpll bit ?0? ?1? ?l? output invalid ?l? output ?l? output pll unlock (except the case above) ?l? output invalid invalid invalid pll lock ?l? output table 9 table 10 1fs output table 7. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) 2) pll slave mode (pmpll b it = ?1?, m/s bit = ?0?) in this mode, an invalid clock is output from the mcko pin before the pll goes to lock state after pmpll bit = ?0? ?1?. then, the clock selected by table 9 is output from the mcko pin when pll is locked. adc and dac output invalid data when the pll is unlocked. the dac outputs can be muted by setting dacl and dacs bits to ?0?. mcko pin pll state mcko bit = ?0? mcko bit = ?1? after pmpll bit ?0? ?1? ?l? output invalid pll unlock (except the case above) ?l? output invalid pll lock ?l? output output table 8. clock operation at pll slave mode (pmpll bit = ?0?, m/s bit = ?0?)
[AK4955] ms1343-e-00 2011/12 - 28 - pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (11.2896mhz, 12mhz, 13.5mhz, 24mhz or 27mhz) is input to the mcki pin, the internal pll circuit generates mcko, bick and lrck clocks. the mcko output frequency is selected by ps1-0 bits ( table 9 ) and switched on and off by mcko bit. the bick output frequency is selected between 32fs or 64fs, by bcko bit ( table 10 ). ak4957 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1f s 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz,12mhz, 13.5mhz, 24mhz, 27mhz mclk figure 18. pll master mode mode ps1 bit ps0 bit mcko pin 0 0 0 256fs (default) 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 9. mcko output frequency (pll mode, mcko bit = ?1?) bcko bit bick output frequency 0 32fs (default) 1 64fs table 10. bick output frequency at master mode
[AK4955] ms1343-e-00 2011/12 - 29 - pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to the mcki or bick pins. the required clock for the AK4955 is generated by an internal pll circuit. input frequency is selected by pll3-0 bits ( table 4 ). a) pll reference clock: mcki pin the bick and lrck inputs must be synchronized with mcko output. the phase between mcko and lrck is not important. the mcko pin outputs the frequency selected by ps1-0 bits ( table 9 ) and the output is enabled by mcko bit. sampling frequency can be selected by fs3-0 bits ( table 5 ) AK4955 dsp or p mcko bick lrck sdto sdti bclk lrck sdti sdto mcki 1fs 32fs 11.2896mhz, 12mhz, 13.5mhz, 24mhz , 27mhz mclk 256fs/128fs/64fs/32fs figure 19. pll slave mode 1 (pll reference clock: mcki pin) b) pll reference clock: bick pin the sampling frequency corresponds to a range fro m 7.35khz to 48khz by changing fs3-0 bits ( table 6 ). AK4955 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs or 64fs figure 20. pll slave mode 2 (pll reference clock: bick pin)
[AK4955] ms1343-e-00 2011/12 - 30 - ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ?0?, the AK4955 becomes ext mode. master clock can be input to the internal adc and dac directly from the mcki pin without internal pll circuit operation. this mode is compatible with i/f of a normal audio codec. the external clocks required to operate this m ode are mcki (256fs, 512fs or 1024fs), lrck (fs) and bick ( 32fs). the master clock (mcki) must be synchronized with lrck. the phase between these clocks is not important. the input frequency of mcki is selected by fs1-0 bits ( table 11 ). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 256fs 7.35khz 48khz (default) 1 x 0 1 1024fs 7.35khz 13khz 2 x 1 0 512fs 7.35khz 26khz 3 x 1 1 512fs 7.35khz 48khz (x: don?t care) table 11. mcki frequency at ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be reduced by using higher frequenc y of the master clock. the s/n of the dac output through lout/rout pins is shown in table 12 . mcki s/n (fs=8khz, 20khzlpf + a-weighted) mode0: 256fs mode3: 512fs 80db mode2: 512fs 92db mode1: 1024fs 92db table 12. relationship between mcki and s/n of lout/rout pins AK4955 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs mclk 256fs, 512fs or 1024fs figure 21. ext slave mode
[AK4955] ms1343-e-00 2011/12 - 31 - ext master mode (pmpll bit = ?0?, m/s bit = ?1?) the AK4955 becomes ext master mode by setting pmpll bit = ?0 ? and m/s bit = ?1?. master clock can be input to the internal adc and dac directly from the mcki pin without the internal pll circuit operation. the external clock required to operate the AK4955 is mcki (256fs, 512fs or 1024fs). the input frequency of mcki is selected by fs1-0 bits ( table 13 ). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 x 0 0 256fs 7.35khz 48khz (default) 1 x 0 1 1024fs 7.35khz 13khz 2 x 1 0 512fs 7.35khz 26khz 3 x 1 1 512fs 7.35khz 48khz table 13. mcki frequency at ext master mode (p mpll bit = ?0?, m/s bit = ?1?) (x: don?t care) the s/n of the dac at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the out-of-band noise can be reduced by using higher frequenc y of the master clock. the s/n of the dac output through lout/rout pins is shown in table 14 . mcki s/n (fs=8khz, 20khzlpf + a-weighted) mode0; 256fs mode3; 512fs 80db mode2; 512fs 92db mode1; 1024fs 92db table 14. relationship between mcki and s/n of lout/rout pins AK4955 dsp or p mcki bick lrck sdto sdti bclk lrck sdti sdto mcko 1fs 32fs or 64fs mclk 256fs, 512fs or 1024fs figure 22. ext master mode bcko bit bick output frequency 0 32fs (default) 1 64fs table 15. bick output frequency at master mode
[AK4955] ms1343-e-00 2011/12 - 32 - system reset upon power-up, the AK4955 must be reset by bringing the pdn pin = ?l?. this reset is released when a dummy command is input after the pdn pin = ?h?. this ensures that all internal registers reset to their initial value. dummy command is executed by writing all ?0? to the register address 00h. it is recommended to set the pdn pin to ?l? before power up the AK4955. csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 c dtio a6 a5 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w: read/write (?1?: write) a6-a0: register address (00h) d7-d0: control data (input), (00h) ?h? or ?l? ?h? or ?l? ?h? o r ?l ? ?h? or ?l? figure 23. dummy command in 3-wire serial mode sda slave address s s t a r t r/w="0" n a c k sub address(00h) n a c k data(00h) n a c k p s t o p figure 24. dummy command in i 2 c-bus mode the adc starts an initialization cycle if the one of pmadl or pmadr is set to ?1? when both of the pmadl and pmadr bits are ?0?. the initialization cycle is set by adrst1-0 bits ( table 16 ). during the initialization cycle, the adc digital data outputs of both channels are forced to ?0? in 2's complement. the adc output reflects the analog input signal after the initialization cycle is fi nished. when using a digital microphone, th e initialization cycle is the same as adc?s. (note) the initial data of adc has offset data that de pends on microphones and the cut-off frequency of hpf. if this offset is not small, make initializati on cycle longer by setting adr st1-0 bits or do not use the first data of adc outputs. init cycle adrst1-0 bits cycle fs = 8khz fs = 16khz fs = 48khz 00 1059/fs 132.4ms 66.2ms 22ms 01 267/fs 33.4ms 16.7ms 5.6ms 10 531/fs 66.4ms 33.2ms 11.1ms (default) 11 135/fs 16.9ms 8.4ms 2.8ms table 16. adc initialization cycle
[AK4955] ms1343-e-00 2011/12 - 33 - audio interface format four types of data formats are available and selected by setting the dif1-0 bits ( table 17 ). in all modes, the serial data is msb first, 2?s complement format. audio interface formats are supported in both master and slave modes. lrck and bick are output from the AK4955 in master mode, but must be input to the AK4955 in slave mode. the sdto is clocked out on the falling edge (? ?) of bick and the sdti is latched on the rising edge (? ?) of bick. mode dif1 bit dif0 bit sdto (adc) sdti (dac) bick figure 0 0 0 24bit msb justified 24bit lsb justified 48fs figure 25 1 0 1 24bit msb justified 16bit lsb justified 32fs figure 26 2 1 0 24bit msb justified 24bit msb justified 48fs figure 27 (default) 3 1 1 i 2 s compatible i 2 s compatible =32fs or 48fs figure 28 table 17. audio interface format lrck bick(64fs) sdto ( o ) 0 1 2 8 9 10 20 21 31 0 1 2 8 9 10 20 21 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 12 11 1 22 0 23 12 11 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 25. mode 0 timing lrck bick ( 64fs ) sdto(o) 0 1 2 3 15 16 17 18 0 1 2 3 15 16 18 17 31 1 sdti ( i ) 23 24 30 23 24 25 23 22 8 13 8 15 14 24bit: 23:msb, 0:lsb 16bit: 15: msb, 0:lsb lch data rch data don?t care 21 5 0 7 6 bick(32fs) sdto ( o ) 0 1 2 3 7 8 9 10 0 1 2 3 15 9 11 10 0 1 sdti(i) 12 13 14 12 13 14 22 21 22 21 10 823 9 15 14 13 12 11 15 23 10 8 9 15 14 13 12 11 8 23 14 13 14 13 2 015 1 7 6 5 4 3 15 2 0 1 7 6 5 4 3 15 0 21 31 23 22 8 13 8 15 14 21 5 0 76 0 2 1 30 don?t care 23 figure 26. mode 1 timing
[AK4955] ms1343-e-00 2011/12 - 34 - lrck bclk(64fs) sdto(o) 0 1 2 18 19 20 21 22 0 1 2 18 19 20 22 21 0 1 sdti(i) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 5 4 1 0 32 10 3 2 23 figure 27. mode 2 timing lrck bick ( 64fs ) sdto(o) 0 1 2 3 19 20 21 22 0 1 2 3 19 20 22 21 0 1 sdti ( i ) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 5 4 1 0 3 2 10 3 2 bick(32fs) sdto ( o ) 0 1 2 3 7 8 9 10 0 1 2 3 15 9 11 10 0 1 sdti(i) 12 13 14 12 13 14 23 22 23 22 11 98 10 16 15 14 13 12 15 8 11 9 10 16 15 14 13 12 8 8 23 22 23 22 11 98 10 16 15 14 13 12 8 11 9 10 16 15 14 13 12 8 figure 28. mode 3 timing
[AK4955] ms1343-e-00 2011/12 - 35 - mono/stereo mode pmadl, pmadr, pmdml and pmdmr bits set mono/stereo adc operation. when changing adc operation and analog/digital microphone, pmadl, pmadr, pmdml and pmdmr bits must be set ?0? at first. when pmdml or pmdmr bit = ?1?, pmadl and pmadr bit settings are ignored. pmadl bit pmadr bit adc lch data adc rch data 0 0 all ?0? all ?0? (default) 0 1 rch input signal rch input signal 1 0 lch input signal lch input signal 1 1 lch input signal rch input signal table 18. mono/stereo adc operation (analog mic) pmdml bit pmdmr bit adc lch data adc rch data 0 0 all ?0? all ?0? (default) 0 1 rch input signal rch input signal 1 0 lch input signal lch input signal 1 1 lch input signal rch input signal table 19. mono/stereo adc operation (digital mic) mic/line input selector the AK4955 has an input selector. inl and inr bits select lin1/lin2 and rin1/rin2, respectively. when dmic bit = ?1?, digital microphone input is selected regardless of inl and inr bits. dmic bit inl bit inr bit lch rch 0 0 lin1 rin1 (default) 0 1 lin1 rin2 1 0 lin2 rin1 0 1 1 lin2 rin2 1 x x digital microphone table 20. mic/line in path select (x: don?t care) mic gain amplifier the AK4955 has a gain amplifier for microphone input. the gain of mic-amp is selected by the mgain3-0 bits ( table 21 ). the typical input impedance is 33k . mgain3 bit mgain2 bit mgain1 bit mgain0 bit input gain 0 0 0 0 0db 0 0 0 1 +5db 0 0 1 0 +8db 0 0 1 1 +11db 0 1 0 0 +14db 0 1 0 1 +16db 0 1 1 0 +18db (default) 0 1 1 1 +21db 1 0 0 0 +24db others n/a table 21. input gain (n/a: not available)
[AK4955] ms1343-e-00 2011/12 - 36 - mic power when pmmp bit = ?1?, the mpwr pin supplies the power for microphones. this output voltage is typically 2.5v @micl bit =?0? (avdd=2.9~3.6v), and typically 2.2v@mic l bit = ?1? (avdd=2.7v~3.6v) . the load resistance is minimum 0.5k . in case of using two sets of stereo microphones, the load resistance is minimum 2k for each channel. any capacitor must not be connected directly to the mpwr pin ( figure 29 ). pmmp bit mpwr pin 0 hi-z (default) 1 output table 22. mic power mpwr pin figure 29. mic block circuit digital mic 1. connection to digital microphones when dmic bit is set to ?1?, the lin1 and rin1 pins become dmdat (digital microphone data input) and dmclk (digital microphone clock supply) pins, respectively. the same voltage as avdd must be provided to the digital microphone. the figure 30 and figure 31 show stereo/mono connection examples. the dmclk clock is input to a digital microphone from the AK4955. the digital microphone outputs 1bit data, which is generated by ? modulator using dmclk clock, to the dmdat pin. pmdml/r bits control power up/down of the digital block (decimation filter and digital filter). (pmadl/pmadr bits settings do not affect the digital mi crophone power management. set pmmp = pmmicl/r bits to ?0? when using a digital microphone.) the dclke bit controls on/off of the output clock from the dmclk pin. when the AK4955 is powered down (pdn pin= ?l?), the dmclk and dmdat pins become floating state. pull-down resistors must be connected to dmclk and dmdat pins externally to avoid this floating state.
[AK4955] ms1343-e-00 2011/12 - 37 - amp ? modulator dmdat dmclk ( 64fs ) pll mc ki sdto vdd AK4955 avdd 100k r amp ? modulator vdd lc h rch decimation filter alc programmable fil ter hpf1 dsp dsp figure 30. connection example of stereo digital mic amp ? modulator dmdat dmclk ( 64fs ) pll mcki sdto vdd AK4955 avdd 1 00 k r decimation filter alc programmable filter hpf1 dsp dsp figure 31. connection example of mono digital mic
[AK4955] ms1343-e-00 2011/12 - 38 - 2. interface the input data channel of the dmdat pin is set by dclkp bit. when dclkp bit = ?1?, l channel data is input to the decimation filter if dmclk = ?h?, and r channel data is input if dmclk = ?l?. when dclkp bit = ?0?, r channel data is input to the decimation filter while dmclk pin= ?h?, and l channel data is input while dmclk pin= ?l?. the dmclk pin only supports 64fs. it outputs ?l? when dclke bit = ?0?, and outputs 64fs when dclke bit = ?1?. in this case, necessary clocks must be supplied to the AK4955 for adc operation. the output data through ?the decimation and digital filters? is 24bit full scale when the 1bit data density is 0%~100%. dclkp bit dmclk pin= ?h? dmclk pin= ?l? 0 rch lch (default) 1 lch rch table 23. data in/output timing with digital mic (dclkp bit = ?0?) dmclk(64fs) dmdat (lch) valid data valid data valid data valid data dmdat (rch) valid data valid data valid data valid data figure 32. data in/output timing with digital mic (dclkp bit = ?1?) dmclk(64fs) dmdat (lch) valid data valid data valid data valid data dmdat (rch) valid data valid data valid data valid data figure 33. data in/output timing with digital mic (dclkp bit = ?0?)
[AK4955] ms1343-e-00 2011/12 - 39 - digital block the digital block consists of the blocks shown in figure 34 . recording path and playback path are selected by setting adcpf bit, pfdac bit, pfsdo bit and dspbp bit. ( figure 35 ~ figure 41 , table 24 ) sdti hpfad bit pmadl/r bit pfdac bit ?0? mono1-0 bits : dsp block dem1-0 bits dvol7-0 bits smute bit ?1? ?0? pmpfil bit a dcpfbit ?1? pmdsp bit 1st order hpf1 adc pmdac bit sdto pmdsp bit pmadl/r bit ?1? dspbp bit ?0? dsp ?1? pfsdo bit ?0? pmpfil bit dac dvol de-emphasis mono/stero switch smute dsp 1st order lpf lpf bit alc bits eq1 bit pmpfil bit ?1? dspbpbit ?0? 1st order hpf3 hpf bit fil3 bit stereo emphasis eq0 bit gn1-0 bits gain compensation eq5-2 bit 4 band eq alc (volume) 1 band eq (1) adc: includes the digital filter (lpf) for adc as shown in ?filter chracteristics?. (2) hpf1: high pass filter (hpf) for adc as shown in ? digital hpf1 ?. (3) hpf3: high pass filter (? digital programmable filter circuit ?) (4) lpf: low pass filter (see ? digital programmable filter circuit ?) (5) gain compensation: gain compensation consists of eq a nd gain control. it corrects frequency characteristics after stereo separation emphasis filter. (see ? digital programmable filter circuit ?) (6) 4 band eq: applicable for use as equalizer or notch filter. (see ? digital programmable filter circuit ?) (7) stereo emphasis: stereo emphasis filter (see ? digital programmable filter circuit ?) (8) alc (volume): digital volume with alc function. (see ? input digital volume ? and ? alc operation ?) (9) 1 band eq: applicable for use as a notch filter (see ? digital programmable filter circuit ?) (10) dvol: digital volume for playback path (see ? output digital volume2 ? ) (11) smute: soft mute function (12) mono/stereo switching: mono/stereo lineout outputs select from dac which described in at ? stereo line outputs ?. (13) de-emphasis: de-emphasis filter (see ? de-emphasis filter control ?) figure 34. digital block path select
[AK4955] ms1343-e-00 2011/12 - 40 - mode adcpf bit pfdac bit pfsdo bit dspbp bit figure recording mode 1 1 0 1 0 figure 35 playback mode 1 0 1 0 0 figure 36 recording mode 2 1 0 1 1 figure 37 playback mode 2 0 1 0 1 figure 38 recording mode 3 & playback mode 3 x 0 0 x figure 39 loopback 1 1 1 1 0 figure 40 loopback 2 1 1 1 1 figure 41 table 24. recording playback mode (x: don?t care) when changing those modes, pmpfil bit must be ?0?. adc alc (volume) 1 band eq 1st order hpf1 dac smute mono dem dvol dsp 4 band eq 1st order lpf stereo separation gain compensation 1st order hpf3 dsp figure 35. the path in recording mode 1 adc 1st order hpf1 alc (volume) stereo separation gain compensation dsp 1st order lpf 1 band eq dac smute mono dem dvol 1st order hpf3 4 band eq dsp figure 36. the path in playback mode 1
[AK4955] ms1343-e-00 2011/12 - 41 - dac adc smute 1st orde r hpf1 mono dem dvol alc (volume) 1 band eq 4 band eq 1st order lpf stereo separation gain compensation 1st orde r hpf3 figure 37. the path in recording mode 2 adc 1st order hpf1 alc (volume) 4 band eq stereo separation gain compensation 1st order lpf 1 band eq dac mono dem dvol smute 1st order hpf3 figure 38. the path in playback mode 2 adc 1st order hpf1 dac smute mono dem dvol figure 39. the path in recording mode 3 & playback mode 3 dsp adc 1st order hpf1 dac smute mono dem dvol alc (volume) 4 band eq 1st order lpf stereo separation gain compensation 1st order hpf3 1 band eq dsp figure 40. the path in loopback mode 1 adc 1st order hpf1 dac smute mono dem dvol alc (volume) 1 band eq 4 band eq 1st order lpf stereo separation gain compensation 1st orde r hpf3 figure 41. the path in loopback mode 2
[AK4955] ms1343-e-00 2011/12 - 42 - digital hpf1 a digital high pass filter (hpf) is integrated for dc offset cancellation of the adc input. the cut-off frequencies of the hpf1 are set by hpfc1-0 bits ( table 25 ). it is proportional to the sampling frequenc y (fs) and the default value is 3.7hz (@fs = 48khz). hpfad bit controls the on/off of the hpf1 (hpf on is recommended). fc hpfc1 bit hpfc0 bit fs=48khz fs=22.05khz fs=8khz 0 0 3.7hz 1.7hz 0.62hz (default) 0 1 14.8hz 6.8hz 2.47hz 1 0 118.4hz 54.4hz 19.7hz 1 1 236.8hz 108.8hz 39.5hz table 25. hpf1 cut-off frequency
[AK4955] ms1343-e-00 2011/12 - 43 - digital programmable filter circuit (1) high pass filter (hpf3) this is composed 1st order hpf. the co efficient of hpf is set by f1a13-0 bits and f1b13-0 bits. hpf bit controls on/off of the hpf3. when the hpf3 is off, the audio data passes this block by 0db gain. the coefficient must be set when pmpfil bit = ?0? or hpf bit = ?0?. the hpf3 starts operation 4/fs (m ax) after when hpf b it=pmpfil bit= ?1? is set. fs: sampling frequency fc: cutoff frequency register setting ( note 42 ) hpf: f1a[13:0] bits =a, f1b[13:0] bits =b (msb=f1a13, f1b13; lsb=f1a0, f1b0) a = 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 ? z ? 1 1 + bz ? 1 the cut-off frequency must be set as below. fc/fs 0.0001 (fc min = 4.8hz at 48khz) (2) low pass filter (lpf) this is composed with 1st order lpf. f2a13-0 bits and f2b 13-0 bits set the coefficient of lpf. lpf bit controls on/off of the lpf. when the lpf is off, the audio data passes this block by 0db gain. the coefficient must be set when pmpfil bit = ?0? or lpf bit = ?0?. the lpf starts operation 4/fs (max) afte r when lpf bit =pmpfil bit= ?1? is set. fs: sampling frequency fc: cutoff frequency register setting ( note 42 ) lpf: f2a[13:0] bits =a, f2b[13:0] bits =b (msb=f2a13, f1b13; lsb=f2a0, f2b0) a = 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 + z ? 1 1 + bz ? 1 the cut-off frequency must be set as below. fc/fs 0.05 (fc min = 2400hz at 48khz)
[AK4955] ms1343-e-00 2011/12 - 44 - (3) stereo separation emphasis filter (fil3) the fil3 is used to emphasize the stereo separation of ster eo microphone recording data and playback data. f3a13-0 bits and f3b13-0 bits set the filter coefficients of the fil3. when f3as bit = ?0?, the fil3 performs as a high pass filter (hpf), and it performs as a low pass filter (lpf) when f3as bit = ?1?. fil3 bit controls on/off of the fil3. when the stereo separation emphasis filter is off, the audio data passes this block by 0db gain. the coe fficient should be set when fil3 bit or pmpfil bit is ?0?. the fil3 starts operation 4/fs(max) after when fil3 bit =pmpfil bit= ?1? is set. 1) in case of setting fil3 as hpf fs: sampling frequency fc: cutoff frequency k: gain [db] (0db k -10db) register setting ( note 42 ) fil3: f3as bit = ?0?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f3a13, f3b13; lsb=f3a0, f3b0) a = 10 k/20 x 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 ? z ? 1 1 + bz ? 1 2) in case of setting fil3 as lpf fs: sampling frequency fc: cutoff frequency k: gain [db] (0db ?k ? 10db) register setting ( note 42 ) fil3: f3as bit = ?1?, f3a[13:0] bits =a, f3b[13:0] bits =b (msb=f3a13, f3b13; lsb= f3a0, f3b0) a = 10 k/20 x 1 1 + 1 / tan ( fc/fs) b = 1 ? 1 / tan ( fc/fs) 1 + 1 / tan ( fc/fs) , transfer function h(z) = a 1 + z ? 1 1 + bz ? 1
[AK4955] ms1343-e-00 2011/12 - 45 - (4) gain compensation (eq0) gain compensation is used to compensate the frequency respons e and the gain that is changed by the stereo separation emphasis filter. gain compensation is composed of the e qualizer (eq0) and the gain ( 0db/+12db/+24db). e0a15-0 bits, e0b13-0 bits and e0c15-0 bits set the coefficient of eq0. gn1-0 bits set the gain ( table 26). eq0 bit controls on/off of eq0. when eq is off and the gain is 0db, the audio data passes this block by 0db gain. the coefficient should be set when eq0 bit = ?0? or pmpfil bit = ?0?. the eq0 starts operation 4/fs(max ) after when eq0 bit =pmpfil bit= ?1? is set. fs: sampling frequency fc 1 : polar frequency fc 2 : zero-point frequency k: gain [db] (maximum setting is +12db.) register setting ( note 42 ) e0a[15:0] bits =a, e0b[13:0] bits =b, e0c[15:0] bits =c (msb=e0a15, e0b13, e0c15; lsb=e0a0, e0b0, e0c0) a = 10 k/20 x 1 + 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) b = 1 ? 1 / tan ( fc 1 /fs) 1 + 1 / tan ( fc 1 /fs) , c =10 k/20 x 1 ? 1 / tan ( fc 2 /fs) 1 + 1 / tan ( fc 1 /fs) , transfer function h(z) = a + cz ? 1 1 + bz ? 1 gain[db] k fc 1 fc 2 frequency figure 42. eq0 frequency response gn1 bit gn0 bit gain 0 0 0db (default) 0 1 +12db 1 x +24db table 26. gain setting (x: don?t care)
[AK4955] ms1343-e-00 2011/12 - 46 - (5) 4-band equalizer & 1-band equalizer after alc this block can be used as equalizer or notch filter. 4-band equalizers (eq2~eq5) are switched on/off independently by eq2, eq3, eq4 and eq5 bits. eq1 bit controls on/off switching of the equalizer after alc (eq1). when the equalizer is off, the audio data passes this block by 0db gain. e1a15-0 bits, e1b15-0 bits and e1c15-0 bits set the coefficient of eq1. e2a15-0 bits, e2b15-0 bits and e2c15-0 b its set the coefficient of eq2. e3a15-0 bits, e3b15-0 bits and e3c15-0 bits set the coefficient of eq3. e4a15-0 bits, e4b15-0 bits and e4c15-0 bits set the coefficient of eq4. e5a15-0 bits, e5b15-0 bits and e5c15-0 bits set the coefficient of eq5. the eqx (x=1, 2, 3, 4 or 5) coefficient must be set when eqx bit = ?0? or pmpfil bit = ?0 ?. eqx starts operation 4/fs(max) afte r when eqx = pmpfil bit = ?1? is set. fs: sampling frequency fo 1 ~ fo 5 : center frequency fb 1 ~ fb 5 : band width where the gain is 3db different from the center frequency k 1 ~ k 5 : gain ( -1 k n < ?3 ) register setting ( note 42 ) eq1: e1a[15:0] bits =a 1 , e1b[15:0] bits =b 1 , e1c[15:0] bits =c 1 eq2: e2a[15:0] bits =a 2 , e2b[15:0] bits =b 2 , e2c[15:0] bits =c 2 eq3: e3a[15:0] bits =a 3 , e3b[15:0] bits =b 3 , e3c[15:0] bits =c 3 eq4: e4a[15:0] bits =a 4 , e4b[15:0] bits =b 4 , e4c[15:0] bits =c 4 eq5: e5a[15:0] bits =a 5 , e5b[15:0] bits =b 5 , e5c[15:0] bits =c 5 (msb=e1a15, e1b15, e1c15, e2a15, e2b15, e2c15, e3a15, e3b15, e3c15, e4a15, e4b15, e4c15, e5a15, e5b15, e5c15 ; lsb= e1a0, e1b0, e1c0, e2a0, e2b0, e2c0, e3a0, e3b0, e3c0, e4a0, e4b0, e4c0, e5a0, e5b0, e5c0) a n = k n x tan ( fb n /fs) 1 + tan ( fb n /fs) b n = cos(2 fo n /fs) x 2 1 + tan ( fb n /fs) , c n = 1 ? tan ( fb n /fs) 1 + tan ( fb n /fs) , (n = 1, 2, 3, 4, 5) transfer function h(z) = {1 + g 2 x h 2 (z) + g 3 x h 3 (z) + g 4 x h 4 (z) + g 5 x h 5 (z)} x {1+ h 1 (z ) } h n (z) = a n 1 ? z ? 2 1 ? b n z ? 1 ? c n z ? 2 (n = 1, 2, 3, 4, 5) (g 2 , 3, 4, 5 = 1 or g) the center frequency must be set as below. fo n / fs < 0.497 when gain of k is set to ?-1?, this equalizer becomes a notch filter. when eq2 eq5 is used as a notch filter, central frequency of a real notch filter deviates from the above-men tioned calculation, if its central frequency of each band is near. the control soft that is attach ed to the evaluation board has functions that revises a gap of frequency and calculates the coefficient. when its cen tral frequency of each band is near, the central frequency shoul d be revised and confirm the frequency response. note 42. [translation the filter coefficient calcula ted by the equations above from real number to binary code (2?s complement)] x = (real number of filter coefficient calculated by the equations above) x 2 13 x should be rounded to integer, and then should be translated to binary code (2?s complement). msb of each filter coefficient se tting register is sine bit.
[AK4955] ms1343-e-00 2011/12 - 47 - alc operation the alc (automatic level control) is operated by alc bl ock. when adcpf bit is ?1?, the alc circuit operates for recording path, and the alc circuit operates for playback pa th when adcpf bit is ?0?. alc1 bit controls on/off of alc operation at recording path, and alc2 bit cont rols on/off of alc operation at playback path. note 43. in this section, vol means ivl and ivr for recording path, ovl and ovr for playback path. note 44. in this section, alc means alc1 for recording path, alc2 for playback path. note 45. in this section, ref means iref for recording path, oref for playback path. 1. alc limiter operation during alc limiter operation, when either l or r channe l output level exceeds the alc limiter detection level ( table 27 ), the vol value (same value for both l and r) is attenuated automatically by the amount defined by the alc limiter att step ( table 28 ). the vol is then set to the same value for both channels. when zelmn bit = ?0? (zero cross detec tion is enabled), the vol value is ch anged by alc limiter operation at the individual zero crossing points of l channel and r channel, or at the zero crossing timeout. ztm1-0 bits set the zero crossing timeout period of both al c limiter and recovery operation ( table 29 ). when alc output level exceeds full-scale at lfst bit = ?1?, vol values are immediatel y (period: 1/fs) changed in 1step(l/r common). when alc output level is less than full-scale, vol values are changed at the individual zero crossing point of each channels or at the zero crossing timeout. when zelmn bit = ?1? (zero cross detection is disabled), vol value is immediately (per iod: 1/fs) changed by alc limiter operation. attenuation step is fixed to 1 step regardless of the setting of lmat1-0 bits. after completing the attenuate operation, unless alc bit is ch anged to ?0?, the operation repeats when the input signal level exceeds alc limiter detection level. lmth1 bit lmth0 bit alc limiter detection level alc recovery counter reset level 0 0 alc output ? 2.5dbfs ? 2.5dbfs > alc output ? 4.1dbfs (default) 0 1 alc output ? 4.1dbfs ? 4.1dbfs > alc output ? 6.0dbfs 1 0 alc output ? 6.0dbfs ? 6.0dbfs > alc output ? 8.5dbfs 1 1 alc output ? 8.5dbfs ? 8.5dbfs > alc output ? 12dbfs table 27. alc limiter detection le vel/ recovery counter reset level alc1 limiter att step lmat1 bit lmat0 bit alc1 output lmth alc1 output fs alc1 output fs + 6db alc1 output fs + 12db 0 0 1 1 1 1 (default) 0 1 2 2 2 2 1 0 2 4 4 8 1 1 1 2 4 8 table 28. alc limiter att step zero cross time out ztm1 bit ztm0 bit 8khz 16khz 48khz 0 0 128/fs 16ms 8ms 2.7ms (default) 0 1 256/fs 32ms 16ms 5.3ms 1 0 512/fs 64ms 32ms 10.7ms 1 1 1024/fs 128ms 64ms 21.3ms table 29. alc zero crossing timeout period
[AK4955] ms1343-e-00 2011/12 - 48 - 2. alc recovery operation alc recovery operation wait for the wtm2-0 bits ( table 30 ) to be set after completing alc limiter operation. if the input signal does not exceed ?alc rec overy waiting counter reset level? ( table 27 ) during the wait time, alc recovery operation is executed. the vol value is automatically incremented by rgain1-0 bits ( table 31 ) up to the set reference level ( table 32 ) with zero crossing detection which timeout period is set by ztm1-0 bits ( table 29 ). the alc recovery operation is executed in a period set by wtm2-0 bits. if the setting of ztm1-0 bits is longer than wtm2-0 bits and no zero crossing occurs, the alc recovery operation is executed at a period set by ztm1-0 bits. for example, when the current vol value is 30h and rgain1-0 bits are set to ?01?, vol is changed to 32h by auto limiter operation and then the input signal level is gained by 0.75db (=0.375db x 2). when the vol value exceeds the reference level (ref7-0), the vol values are not increased. when ?alc recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc recovery operation starts. alc operations correspond to the impulse noise. when the im pulse noise is input, the alc recovery operation becomes faster than a normal recovery operation. when large noise is input to a micr ophone instantaneously, the quality of small level in the large noise can be improved by this fast recove ry operation. the speed of first recovery operation is set by rfst1-0 bits ( table 34 ). the fast recovery operation is not executed wh en frn bit = ?1? even if an impulse noise is input. alc recovery operation waiting period wtm2 bit wtm1 bit wtm0 bit 8khz 16khz 48khz 0 0 0 128/fs 16ms 8ms 2.7ms (default) 0 0 1 256/fs 32ms 16ms 5.3ms 0 1 0 512/fs 64ms 32ms 10.7ms 0 1 1 1024/fs 128ms 64ms 21.3ms 1 0 0 2048/fs 256ms 128ms 42.7ms 1 0 1 4096/fs 512ms 256ms 85.3ms 1 1 0 8192/fs 1024ms 512ms 170.7ms 1 1 1 16384/fs 2048ms 1024ms 341.3ms table 30. alc recovery operation waiting period rgain1 bit rgain0 bit gain step 0 0 1 step 0.375db (default) 0 1 2 step 0.750db 1 0 3 step 1.125db 1 1 4 step 1.500db table 31. alc recovery gain step
[AK4955] ms1343-e-00 2011/12 - 49 - iref7-0 bits gain (db) step f1h +36.0 f0h +35.625 efh +35.25 : : e1h +30.0 (default) : : 92h +0.375 91h 0.0 90h ? 0.375 : : 0.375db 2h ? 53.625 1h ? 54.0 0h mute table 32. reference level of alc recovery operation for recoding oref5-0 bits gain (db) step 3ch +36.0 3bh +34.5 3ah +33.0 : : 28h +6.0 (default) : : 25h +1.5 24h 0.0 23h ? 1.5 : : 1.5db 2h ? 51.0 1h ? 52.5 0h ? 54.0 table 33. reference level of alc recovery operation for playback rfst1 bit rfst0 bit recovery speed 0 0 double 0 1 quad (default) 1 0 8times 1 1 16times table 34. fast recovery speed setting (frn bit = ?0?)
[AK4955] ms1343-e-00 2011/12 - 50 - 3. the volume at alc operation the volume value during alc operation is reflected in vol7-0 bits. it is possible to check the current volume by reading the register value of vol7-0 bits. this function is only enabled in 3-wire control mode (i2c pin = ?l?). vol7-0 bits gain (db) f1h +36.0 f0h +35.625 efh +35.25 : : c5h +19.5 : : 92h +0.375 91h 0.0 90h ? 0.375 : : 2h ? 53.625 1h ? 54.0 0h mute table 35. value of vol7-0 bits 4. example of alc setting table 36 and table 37 show the examples of the alc setting for recording and playback path. fs=8khz fs=48khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing det ection 0 enable 0 enable frn fast recovery mode 0 enable 0 enable ztm1-0 zero crossing timeout period 01 32ms 11 21.3ms wtm2-0 recovery waiting period *wtm2-0 bits should be the same value or larger value than ztm1-0 bits 001 32ms 100 42.7ms iref7-0 maximum gain at recovery operation e1h +30db e1h +30db ivl7-0, ivr7-0 gain of ivol e1h +30db e1h +30db lmat1-0 limiter att step 00 1 step 00 1 step lfst fast limiter operation 1 on 1 on rgain1-0 recovery gain step 00 1 step 00 1 step rfst1-0 fast recovery speed 01 4 times 01 4 times alc1 alc1 enable 1 enable 1 enable table 36. example of the alc setting (recording)
[AK4955] ms1343-e-00 2011/12 - 51 - fs=8khz fs=48khz register name comment data operation data operation lmth1-0 limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing det ection 0 enable 0 enable frn fast recovery mode 0 enable 0 enable ztm1-0 zero crossing timeout period 01 32ms 11 21.3ms wtm2-0 recovery waiting period *wtm2-0 bits should be the same value or larger value than ztm1-0 bits 001 32ms 100 42.7ms oref5-0 maximum gain at recove ry operation 28h +6db 28h +6db ovl7-0, ovr7-0 gain of vol 91h 0db 91h 0db lmat1-0 limiter att step 00 1 step 00 1 step lfst fast limiter operation 1 on 1 on rgain1-0 recovery gain step 00 1 step 00 1 step rfst1-0 fast recovery speed 01 4 times 01 4 times alc2 alc2 enable 1 enable 1 enable table 37. example of the alc setting (playback) 5. example of registers set-up sequence of alc operation the following registers must not be changed during alc opera tion. these bits must be changed after alc operation is stopped by alc1 bit = alc2 bit= ?0?. alc output is ?0 ? data until the AK4955 becomes manual mode after writing ?0? to alc1 and alc2 bits. lmth1-0, lmat1-0, wtm2-0, ztm1-0, rgain 1-0, ref7-0, zelmn, rfst1-0, lfst, frn bits manual mode * the value of ivol should be the same or smaller than ref?s wr (frn, ztm1-0, wtm2-0, rfst1-0) wr (iref7-0) wr (ivl/r7-0) wr (lfst, zelmn, lmat1-0, lmth1-0; alc1= ?1?) example: limiter = zero crossing enable recovery cycle = 42.7ms@48khz limiter and recovery step = 1 maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc1 bit = ?1? (1) addr=0ah, data=73h (2) addr=0ch, data=e1h (5) addr=0bh, data=a1h (3) addr=0fh&10h, data=e1h alc1 operation wr (rgain1-0) (4) addr=0dh, data=28h figure 43. registers set-up sequence at alc1 operation (recording path)
[AK4955] ms1343-e-00 2011/12 - 52 - input digital volume (manual mode) the input digital volume becomes manual mode when alc1 bit is set to ?0? while adcpf bit is ?1?. this mode is used in the cases shown below. 1. after exiting reset state, when setting up the registers for alc operation (ztm1-0, lmth and etc.) 2. when the registers for alc operation (limiter pe riod, recovery period and etc.) are changed. for example; when the sampling frequency is changed. 3. when ivol is used as a manual volume control. ivl7-0 and ivr7-0 bits set the gain of the volume control ( table 38 ). the ivol value is changed at zero crossing or timeout. the zero crossing timeout period is set by ztm1-0 bits . lch and rch volumes are set individually by ivl7-0 and ivr7-0 bits when ivolc bit = ?0?. ivl7-0 bits control both lch and rch volumes together when ivolc bit = ?1?. when changing the volume, zero cross detection is executed on both lch and rch independently. ivl7-0 bits ivr7-0 bits gain (db) step f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 (default) e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54 0.375db 00h mute table 38. input digital volume setting if ivl7-0 or ivr7-0 bits is written during pmpfil bit = ?0?, ivol operation starts with the written values after pmpfil bit is changed to ?1?. when writing to ivol7-0 bits continually, take an interval of zero crossing timeout period or more. if not, the zero crossing counters are reset at each time and the volume will not be changed. however, when writing the same register values as the previous time, the zero cro ssing counters will not be reset, so that it could be written in an interval less than zero crossing timeout.
[AK4955] ms1343-e-00 2011/12 - 53 - de-emphasis filter a digital de-emphasis filter is available for 32khz, 44.1khz or 48khz sampling rates (tc = 50/15 s) by iir filter and it is controlled by dem1-0 bits. these bits sel ect the input frequency for the filtering. ( table 39 ) dem1 bit dem0 bit mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 39. de-emphasis filter control output digital volume (manual mode) the alc block becomes output digital volume (manual mode) by setting alc2 bit to ?0? when pmpfil = pmdac bits = ?1? and adcpf bit is ?0?. the output digital volume gain is set by the ovl7-0 bit and the ovr7-0 bits ( table 40 ). when the ovolc bit = ?1?, the ovl7-0 b its control both l and r channel volume levels. when the ovolc bit = ?0?, the ovl7-0 bits control l channel volume level and the ovr7- 0 bits control r channel volume level. when changing the volumes, zero cross detection is execute d on both l and r channels independently . the ovol value is changed at zero crossing or timeout. the zero crossing timeout period is set by ztm1-0 bits. ovl7-0 bits ovr7-0 bits gain [db] step f1h +36.0 f0h +35.625 efh +35.25 : : 92h +0.375 91h 0.0 (default) 90h -0.375 : : 0.375db 2h -53.625 1h -54.0 0h mute table 40. output digital volume setting when writing to the ovl7-0 bits and ovr7-0 bits continuously, th e control register should be written in an interval more than zero crossing timeout. if not, the zero crossing counters ar e reset at each time and the volume will not be changed. however, when writing the same register va lues as the previous time, the zero crossi ng counter will not be reset, so that it could be written in an interval less than zero crossing timeout.
[AK4955] ms1343-e-00 2011/12 - 54 - output digital volume 2 the AK4955 has a digital output volume (256 levels, 0.5db step, mute). the volume is included in front of a dac block. the input data of dac is changed from +12 to ?115db or mute. when dvolc bit = ?1?, the dvl7-0 bits control both lch and rch volume levels together. when dvolc bit = ?0?, lch and rch volume levels can be controlled independently by dvl7-0 bits and dvr7-0 bits. this volume has soft transition function. therefore no switching noise occurs during the transition. the dvtm bit set the transition time between set values of dvl7-0 and dvr7-0 bits (from 00h to ffh) as either 256/fs or 1024/fs ( table 42 ). when dvtm bit = ?0?, it takes 1024/fs (21.3ms@fs=48khz) from 00h (+12db) to ffh (mute). dvl7-0 bits dvr7-0 bits gain step 00h +12.0db 01h +11.5db 02h +11.0db : : 18h 0db (default) : fdh ? 114.5db feh ? 115.0db 0.5db ffh mute ( ? ) table 41. output digital volume2 setting dvtm bit transition time between dvl/r7-0 bits = 00h and ffh setting fs=8khz fs=48khz 0 1024/fs 128ms 21.3ms (default) 1 256/fs 32ms 5.3ms table 42. transition time setting of output digital volume2
[AK4955] ms1343-e-00 2011/12 - 55 - soft mute soft mute operation is performed in the digital domain. when the smute bit is set ?1?, the output signal is attenuated by - (?0?) during the cycle set by dvtm bit. when the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the value set by dvl/r7-0 bits from - during the cycle set by dvtm bit. if the soft mute is cancelled within the cycle set by dvtm bit after starting the operation, the attenuation is discontinued and returned to the level set by dvl/r7-0 bits. smute bit attenuation dvl/r7-0 bits - f gd gd (1) (2) (3) analog output (1) dvtm bit dvtm bit figure 44. soft mute function (1) the input signal is attenuated to f (?0?) in the cycle set by dvtm bit. (2) analog output corresponding to digital input has group delay (gd). (3) if soft mute is cancelled before attenuating to f , the attenuation is discounted and returned to the level set by dvl/r7-0 bits within the same cycle.
[AK4955] ms1343-e-00 2011/12 - 56 - mono input and beep generation circuit the AK4955 has the min pin for external signal input and a b eep generation circuit. bpm1-0 bits control beep mode. bpm1 bit bpm0 bit beep mode 0 0 min pin (internal resistance mode) (default) 0 1 min pin (external resistance mode) 1 0 beep generator mode 1 1 n/a table 43. beep mode setting (n/a: not available) 1. mono input (min) pin (bpm1-0 bits = ?00? or ?01?) when bpm1-0 bits = ?00? or ?01?, the input signal to the min pin is output from the speaker amplifier by setting beeps bit to ?1?, and it is output from the stereo lineout amplifier by setting beepl bit to ?1?. bpvcm bit sets the common voltage of min input amplifier. ( table 44 ) when bpvcm bit = ?1?, maximum value is avdd vpp. set beep gain (bplvl3-0 bits) to keep min-amp output amplitude less than 0.1vpp. bpvcm bit min-amp common voltage (typ) 0 1.15v (default) 1 1.65v table 44. common potential setting of min-amp ? internal resistance mode (bpm1-0 bits = ?00?) input beep gain is controlled by bplvl3-0 bits ( table 45 ). in this case an external resistor r i is not necessary. bplvl3 bit bplvl2 bit bplvl1 bit bplvl0 bit beep gain 0 0 0 0 0db (default) 0 0 0 1 ? 6db 0 0 1 0 ? 12db 0 0 1 1 ? 18db 0 1 0 0 ? 24db 0 1 0 1 ? 30db 0 1 1 0 ? 33db 0 1 1 1 ? 36db 1 0 0 0 ? 39db 1 0 0 1 ? 42db table 45. beep output gain setting when bpm1-0 bits = ?00?
[AK4955] ms1343-e-00 2011/12 - 57 - min pin lout / rout pin beepl spp/spn pin beeps min-amp bpm1-0 bits = ?00? figure 45. block diagram of min pin (bpm1-0 bits = ?00?) ? external resistance mode (bpm1-0 bit = ?01?) gain setting of input beep signal is controlled by an external resistor r i . the gain is in inverse proportion to the r i value. ( figure 46 ) gain setting by bplvl3-0 bits is not available. min pin ri lout / rout pin beepl spp / spn pin beeps min-amp bpm1-0 bits = ?01? typ 72k figure 46. block diagram of min pin (bpm1-0 bits = ?01?) min ? spp/spn gain spkg1-0 bits alc2 bit = ?0? alc2 bit = ?1? 00 +6.1db +8.1db (default) 01 +8.1db +10.1db 10 +10.1db +12.1db 11 +12.1db +14.1db table 46. min ? spk output gain lvcm1-0 bits min ? lineout gain 00 ? 1.34db 01 0db 10 +2.50db 11 +3.52db table 47.min ? lineout gain (x: don?t care)
[AK4955] ms1343-e-00 2011/12 - 58 - 2. beep generation circuit (bpm1-0 bits = ?10?) the AK4955 integrates a bepp generation circuit. when pmspk bit = ?1?, the speaker amplifier outputs beep signal by setting pmbpg=beeps bits = ?1?, and the stereo lineout amplifier outputs beep signal by setting pmbpg=beepl bit = ?1? when pm lo bit = ?1?. after outputting the signal during the time set by bpon7-0 bits, the AK4955 stops the output signal during the time set by bpoff7-0 bits ( figure 47 ). the repeat count is set by bptm6-0 bits, and the output level is set by bplvl3-0 bits. when bpcnt bit is ?0?, if bpout bit is wr itten ?1?, the AK4955 outputs the beep for the times of repeat count. when the output is finished, bpout bit is set to ?0? automatically. when bpcnt bit is set to ?1?, the AK4955 outputs the beep in succession regardless of repeat count, on-time and off- time. the output frequency is set by bpfr1-0 bits. < setting parameter > 1) output frequency ( table 48 , table 49 ) 2) on time ( table 51 , table 52 ) 3) off time ( table 53 , table 54 ) 4) repeat count ( table 55 ) 5) output level ( table 56 ) ? bpfr1-0, bpon7-0, bpoff7-0, bptm6-0 and bplvl3-0 bits should be set when bpout =bpcnt bits = ?0?. ? bpcnt bit is given priority in bpout bit. when bp out bit is ?1?, bpout bit is set to ?0? forcibly by setting bpcnt bit to ?0?. ? in the case that beep is output by bpcnt bit = ?1?, after stopping the beep outputs by changing bpcnt bit to ?0?, writings to bpou t bit and bpcnt bit are inhibited for 10ms. in the case that beep is output by bpcnt bit = ?0?, after changing bpcnt bit to ?0? or beep output is finished (on/off time and repeat setti ng time), writings to bpout bit and bpcnt bit are inhibited for 10ms. beep output on time off time repeat count figure 47. beep output
[AK4955] ms1343-e-00 2011/12 - 59 - output frequency of beep generator [hz] bpfr1-0 bits fs = 48khz ( note 46 ) fs = 44.1khz ( note 47 ) 00 4000 4009 (default) 01 2000 2005 10 1297 1297 11 800 802 note 46. the sampling frequency is 8khz, 16khz, 32khz, or 48khz. note 47. the sampling frequency is 11.025khz, 22.05khz, or 44.1khz. table 48. beep output frequency (mcki reference, pll master/slave mode) output frequency of beep generator [hz] bpfr1-0 bits fs3-2 bits = ?00? fs3-2 bits = ?01? fs3-2 bits = ?10? 00 fs/2.75 fs/5.5 fs/11 (default) 01 fs/5.5 fs/11 fs/22 10 fs/8.5 fs/17 fs/34 11 fs/13.75 fs/27.5 fs/55 table 49. beep output frequency (bick reference, pll slave mode) output frequency of beep generator [hz] bpfr1-0 bits fs1-0 bits = ?00? fs1-0 bits = ?01? fs1-0 bits = ?10? fs1-0 bits = ?11? 00 fs/11 fs/2.75 fs/5.5 fs/11 (default) 01 fs/22 fs/5.5 fs/11 fs/22 10 fs/34 fs/8.5 fs/17 fs/34 11 fs/55 fs/13.75 fs/27.5 fs/55 table 50. beep output frequency (ext master/slave mode) on time of beep generator [msec] step[msec] bpon7-0 bits fs=48khz ( note 46 ) fs=44.1khz ( note 47 ) fs=48khz ( note 46 ) fs=44.1khz ( note 47 ) 0h 8.0 7.98 8.0 7.98 (default) 1h 16.0 15.86 2h 24.0 23.95 3h 32.0 31.93 : : : fdh 2032 2027.3 feh 2040 2035.3 ffh 2048 2043.4 note 46. the sampling frequency is 8khz, 16khz, 32khz, or 48khz note 47. the sampling frequency is 11.025khz, 22.05khz, or 44.1khz table 51. beep output on time (mcki reference, pll master/slave mode)
[AK4955] ms1343-e-00 2011/12 - 60 - on time of beep generator [msec] step[msec] bpon7-0 bits fs=48khz ( note 46 ) fs=44.1khz ( note 47 ) fs=48khz ( note 46 ) fs=44.1khz ( note 47 ) 0h 7.33 7.98 7.33 7.98 (default) 1h 14.67 15.86 2h 22.00 23.95 3h 29.33 31.93 : : : fdh 1862.6 2027.3 feh 1970.0 2035.3 ffh 1877.3 2043.4 note 46. the sampling frequency is 8khz, 16khz, 32khz, or 48khz note 47. the sampling frequency is 11.025khz, 22.05khz, or 44.1khz table 52. beep output on time (bick reference, pll slave mode, ext master/slave mode) off time of beep generator [msec] step[msec] bpoff7-0 bits fs=48khz ( note 46 ) fs=44.1khz ( note 47 ) fs=48khz ( note 46 ) fs=44.1khz ( note 47 ) 0h 8.0 7.98 8.0 7.98 (default) 1h 16.0 15.86 2h 24.0 23.95 3h 32.0 31.93 : : : fdh 2032 2027.3 feh 2040 2035.3 ffh 2048 2043.4 note 46. the sampling frequency is 8khz, 16khz, 32khz, or 48khz note 47. the sampling frequency is 11.025khz, 22.05khz, or 44.1khz table 53. beep output off time (mcki reference, pll master/slave mode) off time of beep generator [msec] step[msec] bpoff7-0 bits fs=48khz ( note 46 ) fs=44.1khz ( note 47 ) fs=48khz ( note 46 ) fs=44.1khz ( note 47 ) 0h 7.33 7.98 7.33 7.98 (default) 1h 14.67 15.86 2h 22.00 23.95 3h 29.33 31.93 : : : fdh 1862.6 2027.3 feh 1970.0 2035.3 ffh 1877.3 2043.4 note 46. the sampling frequency is 8khz, 16khz, 32khz, or 48khz note 47. the sampling frequency is 11.025khz, 22.05khz, or 44.1khz table 54. beep output off time (bick reference, pll slave mode, ext master/slave mode)
[AK4955] ms1343-e-00 2011/12 - 61 - bptm6-0 bits repeat count 0h 1 (default) 1h 2 2h 3 : : 7dh 126 7eh 127 7fh 128 table 55. beep output repeat count bplvl3 bit bplvl2 bit bplvl1 bit bplvl0 bit beep gain 0 0 0 0 0db (default) 0 0 0 1 ? 6db 0 0 1 0 ? 12db 0 0 1 1 ? 18db 0 1 0 0 ? 24db 0 1 0 1 ? 30db 0 1 1 0 ? 33db 0 1 1 1 ? 36db 1 0 0 0 ? 39db 1 0 0 1 ? 42db note 48. when the beep gain is set to 0db, beep output amplitude is 2.3vpp at lineout and 3.0vpp at spk-amp with 8 ? (spkg1-0 bits = ?00?). table 56. beep output level
[AK4955] ms1343-e-00 2011/12 - 62 - stereo line output (lout, rout pin) when dacl bit is set to ?1?, l and r channel signals of dac are output in single-ended format via lout and rout pins. when dacl bit is ?0?, output signals are muted and lout and rout pins output common voltage. the load impedance is 10k (min.). when the pmlo bit = lops bit = ?0?, the stereo line output enters power-down mode and the output is pulled-down to vss1 by 100k (typ). when the lops bit is ?1?, stereo line output enters power-save mode. pop noise at power-up/down can be reduced by changing pmlo bit when lops bit = ?1?. in this case, output signal line should be pulled-down by 20k after ac coupled as figure 49 . rise/fall time is 300ms (max) when c=1 f and r l =10k . when pmlo bit = ?1? and lops bit = ?0?, stereo line output is in normal operation. lvcm1-0 bits set the gain of stereo line output. dac ?dacl bit? lout pin rout pin ?lvcm1-0 bits? figure 48. stereo line output lops bit pmlo bit mode lout/rout pin 0 power down pull-down to vss1 (default) 0 1 normal operation normal operation 0 power save fall down to vss1 1 1 power save rise up to common voltage table 57. stereo line output mode select lvcm1-0 bits lvdd gain 00 2.7 ~ 5.5 v ? 1.34db (default) 01 3.0 ~ 5.5 v 0db 10 4.0 ~ 5.5 v +2.50db 11 4.5 ~ 5.5v +3.52db table 58. stereo lineout volume setting lout rout 1 f 220 20k figure 49. external circuit for stereo line output (in case of using a pop noise reduction circuit)
[AK4955] ms1343-e-00 2011/12 - 63 - [stereo line output control sequence (in case of using a pop noise reduction circuit)] pmlo bit lops bit lout, rout pins (1) (2) normal output (3) (4) (5) (6) 300 ms 300 ms 99% common voltage 1% common voltage figure 50. stereo line output control sequence (in case of using a pop noise reduction circuit) (1) set lops bit = ?1?. stereo line output enters power-save mode. (2) set pmlo bit = ?1?. stereo line output exits power-down mode. lout and rout pins rise up to common voltage. rise time is 200ms (max 300ms) when c=1 f. (3) set lops bit = ?0? after lout and rout pins rise up. stereo line output exits power-save mode. stereo line output is enabled. (4) set lops bit = ?1?. stereo line output enters power-save mode. (5) set pmlo bit = ?0?. stereo line output enters power-down mode. lout and rout pins fall down to 1% of the common voltage. fall time is 200ms (max 300ms) at c=1 f. (6) set lops bit = ?0? after lout and rout pins fall down. stereo line output exits power-save mode. < mono mixing output > mono mixing outputs are available by setting mono1-0 bits. inputted digital data from the sdti pin can be converted to mono signal [(l+r)/2] and are output via lout and rout pins. ( figure 34 ) mono1 bit mono0 bit lout pin rout pin 0 0 lch rch (default) 0 1 lch lch 1 0 rch rch 1 1 (lch+rch)/2 (lch+rch)/2 table 59. output data select via lout/rout pin
[AK4955] ms1343-e-00 2011/12 - 64 - speaker output the dac output signal is input to the speaker amplifier as mono signal [(l+r)/2]. the speaker amplifier has mono output as it is blt (bridged transless) capable. the gain and output level are set by spkg1-0 bits. the output level is depends on avdd and spkg1-0 bits setting. gain spkg1-0 bits alc bit = ?0? alc bit = ?1? 00 +6.1db +8.1db (default) 01 +8.1db +10.1db 10 +10.1db +12.1db 11 +12.1db +14.1db table 60. spk-amp gain spk-amp output (dac input =0dbfs) svdd spkg1-0 bits alc bit = ?0? alc bit = ?1? (lmth1-0 bits = ?00?) 00 3.37vpp 3.17vpp 01 4.23vpp ( note 49 ) 4.00vpp 10 5.33vpp ( note 49 ) 5.04vpp ( note 49 ) 3.3v 11 6.71vpp ( note 49 ) 6.33vpp ( note 49 ) 00 3.37vpp 3.17vpp 01 4.23vpp 4.00vpp 10 5.33vpp 5.04vpp 4.8v 11 6.71vpp ( note 49 ) 6.33vpp ( note 49 ) note 49. the output level is calculated on the assumption that the signal is not clipped. however, in the actual case, the spk-amp output signal is clipped when dac outputs 0dbfs signal. the spk-amp output level should be kept under 4.0vpp (avdd=3.3v) or 6.0vpp (svdd=4.8v) by adju sting digital volume to prevent clipped noise. table 61. spk-amp output level
[AK4955] ms1343-e-00 2011/12 - 65 - < speaker-amp control sequence > the speaker amplifier is powered-up/down by pmspk bit. when pmspk bit is ?0 ?, both spp and spn pins are in hi-z state. when pmspk bit is ?1? and sppsn b it is ?0?, the speaker amp lifier enters power-save mode. in this mode, the spp pin is placed in hi-z state and the spn pin outputs svdd/2 voltage. when the pmspk bit is ?1? after the pdn pin is changed fro m ?l? to ?h?, the spp and spn pins rise up in power-save mode. in this mode, the spp pin is placed in a hi-z stat e and the spn pin goes to svdd/2 voltage. because the spp and spn pins rise up in power-save mode, pop noise can be reduced. when the AK4955 is powered-down (pmspk bit = ?0?), pop noise can also be reduced by first entering power-save-mode. pmspk bit sppsn bit mode spp pin spn pin 0 x power-down hi-z hi-z (default) 0 power-save hi-z svdd/2 1 1 normal operation normal operation normal operation table 62 speaker-amp mode setting (x: don?t care) pmspk bit sppsn bit spp pin spn pin svdd/2 svdd/2 hi-z hi-z >1ms ( recommended value) > 0 hi-z hi-z ( recommended value) figure 51. power-up/power-down timing for speaker-amp thermal shutdown function when the internal temperature of the device rises up irregularly (e.g. when output pins are shortened), the thermal shutdown is executed, all blocks except vcom and ldo bloc ks are powered-down, and t hdet bit becomes ?1?. these blocks will not return to normal operation until being reset by the pdn pin. the thermal shutdown status can be monitored by reading thdet bit. thdet bit becomes ?0? by this pdn pin reset.
[AK4955] ms1343-e-00 2011/12 - 66 - video block the integrated cap-less video amplifier with a charge pump has drivability for a load resistance of 150 ( figure 52 ). the AK4955 has a composite input a nd output. a low pass filter (lpf) and gain control amp are integrated, and vg1-0 bits set the gain (+6/+9/+12/16.5 db) ( table 63 ).the integrated charge pump circuit supplies a negative power to the video amplifier, and the video amplifier outputs 0v video signal as pedestal level. the video amplifier power management is controlled by pmv bit, and the charge pump ci rcuit power management is controlled by pmcp bit. when pmv bit = ?0?, the vout pin outputs 0v. the video inputs must be c-coupled by a 0.1 f capacitor. the video signal source impedance at transmitting side must be less than or equal to 600 . vin clamp lpf vout clock generator vss1 pvee pmcp bit charge pump pmv bit +6/+9/+12/+16.5db typ 0.1 f max 600 2.2 f figure 52. video block diagram vg1-0 bits gain 00 +6db (default) 01 +9db 10 +12db 11 +16.5db table 63. video signal gain setting vout 75 a k4955 0v 75 figure 53. video signal output
[AK4955] ms1343-e-00 2011/12 - 67 - regulator block the AK4955 integrates a regulator. the 3.3v (typ) power supply voltage from the avdd pin is converted to 2.3v (typ) by the regulator and supplied to the analog blocks (mic-amp, adc, dac, min, video-amp). the regulator is powered up by pmvcm bit = ?1?, and powered down by pmvcm = ?0?. connect a 2.2f ( 50%) capacitor to the regfil pin to reduce noise on avdd. AK4955 avdd to analog block regulator typ 2.3v regfil 2.2 f 50% power-up: pmvcm bit =?1? power-down: pmvcm bit = ?0? figure 54 regulator block
[AK4955] ms1343-e-00 2011/12 - 68 - serial control interface (1) 3-wire serial control mode (00h ~ 4fh) 1. data writing and reading modes on every address (00h~4fh) one data is written to (read from) one address. internal registers may be written by using 3-wire serial inte rface pins (csn, cclk and cdtio). the data on this interface consists of read/write, register address (msb first, 7bits) a nd control data or output data (msb first, 8bits). address and data is clocked in on the rising edge of cclk and data is clocked out on th e falling edge. data writings become available on the rising edge of csn. when reading the data, the cdtio pin changes to output mode at the falling edge of 8th cclk and outputs data in d7-d0. however this reading function is available only when read bit = ?1?. when read bit = ?0?, the cdtio pin stays as hi-z even after the falling edge of 8th cclk. the data output finishes on the rising edge of csn. the cdtio is placed in a hi-z st ate except when outputting the da ta at read operation mode. clock speed of cclk is 12.5mhz (max) when writing and 6.75mhz (max) when reading. the value of internal registers are initialized by the pdn pin = ?l?. note 50. data reading is only available on the following addr esses; 00 ~ 4fh and 50h ~ 6fh. when reading address 50h ~ 6fh, the register values are invalid. csn cclk 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 c dtio a6 a5 a2 a3 a1 a0 a4 d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w: read/write (?1?: write, ?0?: read) a6-a0: register address d7-d0: control data (input) at write command output data (output) at read command ?h? or ?l? ?h? or ?l? ?h? o r ?l ? ?h? or ?l? figure 55. serial cont rol interface timing 1
[AK4955] ms1343-e-00 2011/12 - 69 - 2. continuous data wr iting mode (00h~4fh) address is incremented automatically and data is written continuously. this mode does not support reading. when the written address reaches 4fh, it is auto matically incremented to 00h. writing to the address 0eh and 31h are ignored. in this mode, registers are written by 3- wire serial interface pins (csn, cclk and cdtio). the data on the 3-wire serial interface is 8 bit data, consisting of regi ster address (msb-first, 7b its) and control or output da ta (msb-first, 8xn bits)). the receiving data is la tched on a rising edge (? ?) of cclk. the first write data becomes effective between the rising edge (? ?) and the falling edge (? ?) of 16th cclk. when the micro processor continues sending cdti and cclk clocks while the csn pin = ?l?, the address counter is in cremented automatically and wr iting data becomes effective between the rising edge (? ?) and the falling edge (? ?) of every 8th cclk. for the last address, writing data becomes effective between the rising edge (? ?) of 8th cclk and the rising edge (? ?) of csn. the clock speed of cclk is 12.5mhz (max). the internal registers are initialized by the pdn pin = ?l?. even through the writing data does not reach the last address; a write command can be completed when the csn pin is set to ?h?. note 51. when csn ? ? was written before ? ? of 8th cclk in continuous data wr iting mode, the previous data writing address becomes valid and the writing address is ignored. note 52. after 8bits data in the last address became valid , put the csn pin ?h? to complete the write command. if the cdti and cclk inputs are continued when the csn pin = ?l?, the data in the next address, which is incremented, is over written. csn cclk 0 1 2 3 4 5 6 7 8 9 14 15 0 1 cdti r/w a6 a2 a3 a1 a0 a4 d7 d6 d1 d0 d7 d6 a5 6 d1 d0 7 0 1 d7 d6 6 d1 7 d0 clock, ?h? or ?l? ?h? or ?l? clock, ?h? or ?l? ?h? or ?l? address: n data (addr: n) data (addr: n+1) data (addr: n+n-1) r/w: read/write (?1?: write, ?0?: read) a6-a0: register address d7-d0: control data (input) at write command output data (output) at read command figure 56. serial control interf ace timing 2 (continuous writing mode)
[AK4955] ms1343-e-00 2011/12 - 70 - (2) i2c-bus control mode (i2c pin = ?h?) the AK4955 supports the fast-mode i 2 c-bus (max: 400khz). pull-up resistors at the sda and scl pins must be connected to 6v or less voltage. (2)-1. write operations figure 57 shows the data transfer sequence for the i 2 c-bus mode. all commands are pr eceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition ( figure 70 ). after the start condition, a slave address is sent. this address is 7 bits long followed by the eighth bit that is a data direction bit (r/w). the most significant six bits of the slave address are fixed as ?001001?. the next bit is cad0 (device address bit). this bit identifies the specific device on the bus. the hard-wired input pin (cad0 pin) sets these device address bits ( figure 58 ). if the slave address matches that of the AK4955, the AK4955 generates an acknowledge and the operation is executed. the master must generate the acknowledge-relate d clock pulse and release the sda line (high) during the acknowledge clock pulse ( figure 71 ). a r/w bit value of ?1? indicates that th e read operation is to be executed, and ?0? indicates that the write operation is to be executed. the second byte consists of the control register address of the AK4955. the format is msb first, and those most significant 1bit is fixed to zero ( figure 59 ). the data after the second byte contains control data. the format is msb first, 8bits ( figure 60 ). the AK4955 generates an acknowledge after each byte is received. data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition ( figure 70 ). the AK4955 can perform more than one by te write operation per sequence. after receipt of the third byte the AK4955 generates an acknowledge and awaits the next data. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. afte r receiving each data packet the internal address counter is incremented by one, and the next data is automatically taken into the next address. if the address exceeds ?4fh? prior to generating a stop condition, the address counter will ?roll over? to 00h and th e previous data will be overwritten. the data on the sda line must remain stable during the high period of the clock. high or low state of the data line can only be changed when the clock signal on the scl line is low ( figure 72 ) except for the start and stop conditions. sda slave address s s t a r t r/w="0" a c k sub address(n) a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p figure 57. data transfer sequence at i 2 c bus mode 0 0 1 0 0 1 cad0 r/w figure 58. the first byte 0 a6 a5 a4 a3 a2 a1 a0 figure 59. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 60. the third byte
[AK4955] ms1343-e-00 2011/12 - 71 - (2)-2. read operations set the r/w bit = ?1? for the read operation of the AK4955. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cy cle after the receipt of the first data word. after receiving each data packet the intern al address counter is incremented by one , and the next data is automatically taken into the next address. if the address exceeds 4fh prio r to generating stop condition, the address counter will ?roll over? to 00h and the data of 00h will be read out. note 50. data reading is only available on the following addr esses; 00 ~ 4fh and 50h ~ 6fh. when reading address 50h ~ 6fh, the register values are invalid. the AK4955 supports two basic read operations: current address read and random address read. (2)-2-1. current address read the AK4955 has an internal address counter that maintains the address of the last accessed word incremented by one. therefore, if the last access (either a read or write) were to address ?n?, the next current read operation would access data from the address ?n+1?. after receipt of the slave address with r/w bit ?1?, the AK4955 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknow ledge but generates a stop condition instead, the AK4955 ceases the transmission. sda slave address s s t a r t r/w="1" a c k a c k data(n+1) a c k data(n+2) a c k a c k data(n+x) n a c k p s t o p data(n) m a s t e r m a s t e r m a s t e r m a s t e r m a s t e r figure 61. current address read (2)-2-2. random address read the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. th e master issues a start request, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start request and the slave addr ess with the r/w bit ?1?. the AK4955 then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the AK4955 ceases the transmission. sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p sub address(n) s slave address r/w="1" s t a r t data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r figure 62. random address read
[AK4955] ms1343-e-00 2011/12 - 72 - serial control interface to dsp (1) dsp access format in 3-wire mode csn cdtio cclk pmdsp bit command address data dummy data data data don?tcare (l/h) don?tcare (l/h) (control register setting is abbreviated) dspstbn bit figure 63. consecutive writing to ram address length is 2byte fixed, and data length is shown below. command address length data length description note f1h 2byte 2byte cram write data during run 2data f2h 2byte 2byte cram write data during run 3data f3h 2byte 2byte cram write data during run 4data f4h 2byte 2byte cram write data during run 5data f5h 2byte 2byte cram write data during run 6data f6h 2byte 2byte cram write data during run 7data f7h 2byte 2byte cram write data during run 8data f8h 2byte 2byte cram write data during run 9data f9h 2byte 2byte cram write data during run 10data fah 2byte 2byte cram write data during run 11data fbh 2byte 2byte cram write data during run 12data fch - 1byte external conditional jump code address input is not necessary when writing to consecutive address during run. e.g. input 2byte x 12 after 2byte address when writing to fbh. if the data is over write limit, it is ignored. fdh 2byte - write execution during run write data should be all ?0?. feh 2byte 2byte cram writing during rst ffh 2byte 5byte pram writing during rst address input is not necessary when writing to consecutive address. these writings are valid when dspstbn bit= ?1? and pmdsp bit = ?0?. if the written data exceeds the allotted amount , pram or cram data is over written. * a 1byte dummy data write (all ?1? or ?0?) is necessary after command, address length and data length writings as shown above when writing to dsp. this dummy data mu st be 2byte when writing to cram during a reset. table 64. list of usable write commands in write sequence
[AK4955] ms1343-e-00 2011/12 - 73 - 1. ram writing timing during run use this operation to rewrite cram during run. after inputting the assigned command code (8-bit) to select the number of data from 2 to 12, input the starting address of write (16-bit all 0) and the number of data assigned by command code in this order (write preparation). upon completion of this operation, execute ram write during run by inputting the corresponding command code and address (16-bit all 0) in this order (write execution). csn cdtio cclk command a ddress rdy(internal) data e.g. when # of data is 3 cram 0xf1(# of data 2) ~ 0xfb (data number 12) cram command 0xf2 don?tcare (l/h) data data dummy don?tcare (l/h) figure 64. cram write preparation
[AK4955] ms1343-e-00 2011/12 - 74 - 2. ram reading timing during rst (when d spstbn bit= ?1? and pmdsp bit= ?0?). csn cdtio cclk pmdsp bit command address wait data data data data don?tcare (l/h) don?tcare (l/h) (control register setting is abbreviated) dspstbn bit figure 65. ram reading timing during rst ram data can be readout during a reset. there is a wait time (1byte) after command code and address inputs when reading ram data. during this wait time, the cdtio pin is in output state and the output data is indefinite. msb data is output on the first falling edge of cclk after the wait time. command code and output data length are shown below. command description address length data length note 7eh cram reading during rst. 2byte 2byte 7fh pram reading during rst. 2byte 5byte only the first read address is necessary when reading from consecutive address data. table 65. command code and output data in ram reading during a rst
[AK4955] ms1343-e-00 2011/12 - 75 - 3. micr reading timing csn cdtio cclk pmdsp bit command wait data data data data don?tcare (l/h) don?tcare (l/h) (control register setting is abbreviated) dspstbn bit data figure 66. micr reading there is a wait time (1byte) after command code and address inputs when reading micr data. during this wait time, the cdtio pin is in output state and the output data is indefinite. msb data is output on the first falling edge of cclk after the wait time. command data length description 70h 4byte micr1 reading 71h 4byte micr2 reading 72h 4byte micr3 reading 73h 4byte micr4 reading table 66. command code and data length when reading mrci 4. written data reading timing during run csn cdtio cclk pmdsp bit command wait data address data data don?tcare (l/h) don?tcare (l/h) (control register setting is abbreviated) dspstbn bit address figure 67. written data reading during run there is a wait time (1byte) after command code and addre ss inputs when reading cram written data. during this wait time, the cdtio pin is in output state and the output data is indefinite. msb data is output on the first falling edge of cclk after the wait time. command address length data length description note fdh 2byte 2byte x n cram written data reading during run n=2~12 table 67. command code and data length reading during run
[AK4955] ms1343-e-00 2011/12 - 76 - (2) dsp access format in i 2 c-bus control mode 1. write operation in the AK4955, when a ?write-slave-address assignment? is received at the first byte, the write command at the second byte and data at the third and succeeding bytes are received. at the data block, address and write data are received in a single-byte unit each in accordance with a command code. the number of write data bytes (*1 in figure 68 ) is fixed by the received command code. data writings must be executed after an acknowledge. there are some cases that 2lrck wait time is needed depending on the written command. a 1byte dummy command (all ?0? or ?1?) must be written after inputting the data. figure 68. write sequence to dsp command address length data length content f1h ~ fbh 2byte assignment 2byte assignment n (n=2~12) cram write preparation during run. lsb 4bits of the command code assign the number of write operation. (f1h: 2, ? fbh: 12) write operation exceeding the assigned number of write, abandons the data. fch none 1byte assignment external conditional jump code input fdh 2byte assignment none cram writing during run. the address is all ?0? input. feh 2byte assignment 2byte assignment n cram writing during a system reset. ffh 2byte assignment 2byte assignment n pram writing during a system reset. note: length of write data is variable with the areas to be written. when accessing ram, it is possible to write data at sequential address locations by writing data continuously. writing command codes other than above are prohibited. table 68. list of usable write command codes in write sequence slave address s start r/w=0 sda command code ack address ack address ack address data is 2byte assignment. no address input if there is no address. ack data ack ~ ~ ~ ~ ~ ~ ack data ack data ~ ~ dummy ack p stop dummy 1byte depending on write data length *1
[AK4955] ms1343-e-00 2011/12 - 77 - 2. read operation random address read operation is only suppor ted when accessing the internal dsp. the random read operation allows the master to access any memo ry location at random. prior to issuing the slave address with the r/w bit ?1?, the master must first perform a ?dummy? write operation. the master issues a start condition, a slave address (r/w bit = ?0?) and then the register address to read. after the register address is acknowledged, the master immediately reissues the start condition and the slave addr ess with the r/w bit ?1?. the AK4955 then generates an acknowledge, 1 byte of data and increments the internal a ddress counter by 1. if the master does not generate an acknowledge but generates a stop condition instead, the AK4955 ceases the transmission. figure 69. random address read from dsp command address length data length content 70h none 4byte @micr0 reading 71h none 4byte @micr1 reading 72h none 4byte @micr2 reading 73h none 4byte @micr3 reading 7dh 2byte assignment 2byte assignment n (n=2~12) cram write preparation data reading during run 7fh 2byte assignment 5byten pram reading during a system reset 7eh 2byte assignment 2byten cram reading during a system reset note 53. length of read data is vari able by command code. as for access to ra m, it is possible to read data at sequential address locations by reading data con tinuously. reading command codes other than above are prohibited. there is a wait time (1byte) after an acknowledge following read commands after the dummy writing. during this wait time, the sda pin is in output state and the output data is indefinite. msb data is output after the first acknowledge following this wait time. table 69. list of usable read command codes in read sequence slave address s start r/w=0 sda command code ack address ack address ack address data is 2byte assignment. no address input if there is no address. ack slave address s start r/w=1 ack wait ack ~ ~ ~ ~ ~ ~ ack master data ack master data ~ ~ data ack master p stop wait 1byte data length is variable with the areas to be read.
[AK4955] ms1343-e-00 2011/12 - 78 - scl sda stop condition start condition s p figure 70. start condition and stop condition scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 71. acknowledge (i 2 c bus) scl sda data line stable; data valid change of data allowed figure 72. bit transfer (i 2 c bus)
[AK4955] ms1343-e-00 2011/12 - 79 - checksum function the AK4955 has a checksum function. when sumrstn bit = ?1?, checksum of writing data is updated. when sumrstn bit = ?0?, the checksu m value is rest to zero. ch ecksum is calculated in 8-bit step. when the checksum value exceeds 255 in decimal format, the values will be subtracted by 256. checksum value can be monitored by reading csum7-0 bits. this function is only valid in 3-wire control mode (i2c pin = ?l?). sumrstn =?0? checksum= 0 =?1? write command? read checksum not updated write updating checksum access to the AK4955 figure 73. flowchart of checksum
[AK4955] ms1343-e-00 2011/12 - 80 - dsp power-up sequence set dspstbn bit to ?1? to supply clock to the dsp after clock is stabilized (p ll lock). program downloadings to the dsp become available by setting dspstbn bit ?0? ?1?. (there is no time limit for dsp program download.) write a program to pram and data to cram. the dsp is powered -up and dram initialization is started by pmdsp bit ?0? ?1?, after downloading a program. dspstbn bit pmpbp bit dram clear (230 s @ dspc bit = ?0? fs = 48khz) dsp program operation start initial power-up sequence wad abbreviated. dram clear dsp start dsp program downloading period figure 74. dsp power-up sequence in the dram clear sequence, it is possible to send commands to the dsp. (dsp is stopped during dram clear sequence. the sent cram write command is accepted automati cally after this sequence is completed.) initialization period of the dram is dependent on dspc bit setting and sampling frequency. maximum 6lrck 125 sec@48khz when dspc bit= ?1? (when dsp=512fs). maximum 11lrck 230 sec@48khz when dspc bit= ?0? (when dsp=256fs).
[AK4955] ms1343-e-00 2011/12 - 81 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmpfil pmvcm pmdsp pmspk pmlo pmdac pmadr pmadl 01h power management 2 sppsn dspstbn pmbpg pmbp m/s sumrstn mcko pmpll 02h signal select 1 pmmicr pmmicl pmmp micl mgain3 mgain2 mgain1 mgain0 03h signal select 2 spkg1 spkg0 beeps dacs 0 0 inr inl 04h signal select 3 mono1 mono2 lops dacl beepl 0 lvcm1 lvcm0 05h mode control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 06h mode control 2 ps1 ps0 ff te dspc fs3 fs2 fs1 fs0 07h mode control 3 read thdet smu te dvolc ovolc ivolc dem1 dem0 08h digital mic 0 0 pmdmr pmdml dclke 0 dclkp dmic 09h timer select adrst1 adrst0 0 0 0 0 0 dvtm 0ah alc timer select frn ztm1 ztm0 wtm2 wtm1 wtm0 rfst1 rfst0 0bh alc mode control 1 lfst alc2 alc1 zelmn lmat1 lmat0 lmth1 lmth0 0ch alc mode control 2 iref7 iref6 iref5 iref4 iref3 iref2 iref1 iref0 0dh alc mode control 3 rgain1 rgain0 oref5 oref4 oref3 oref2 oref1 oref0 0eh alc volume vol7 vol6 vol 5 vol4 vol3 vol2 vol1 vol0 0fh lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 10h rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 11h lch output volume control ovl 7 ovl6 ovl5 ovl4 ovl 3 ovl2 ovl1 ovl0 12h rch output volume control ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 13h lch digital volume control dvl 7 dvl6 dvl5 dvl4 dvl 3 dvl2 dvl1 dvl0 14h rch digital volume control dvr7 dvr6 dvr5 dvr4 dvr3 dvr2 dvr1 dvr0 15h beep control bpcont bpvcm bpm1 bpm0 0 0 bpfr1 bpfr0 16h beep on time bpon7 bpon6 bpon5 bpon4 bpon3 bpon2 bpon1 bpon0 17h beep off time bpoff7 bpoff6 bpoff5 bpoff4 bpoff3 bpoff2 bpoff1 bpoff0 18h beep repeat count 0 bptm6 bptm 5 bptm4 bptm3 bptm2 bptm1 bptm0 19h beep volume control bpout 0 0 0 bplvl3 bplvl2 bplvl1 bplvl0 1ah video control 0 0 0 0 vg1 vg0 pmcp pmv 1bh hpf filter control 0 0 0 0 0 hpfc1 hpfc0 hpfad 1ch digital filter select 1 0 0 lpf hpf eq0 gn1 gn0 fil3 1dh digital filter control 0 0 0 0 dspbf pfdac adcpf pfsdo 1eh hpf3 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1fh hpf3 co-efficient 1 0 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 20h hpf3 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 21h hpf3 co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 22h lpf co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 23h lpf co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 24h lpf co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 25h lpf co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8 26h fil3 co-efficient 0 f3a7 f3a6 f3 a5 f3a4 f3a3 f3 a2 f3a1 f3a0 27h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 28h fil3 co-efficient 2 f3b7 f3b6 f3 b5 f3b4 f3b3 f3b2 f3b1 f3b0 29h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 2ah eq0-efficient 0 e0a7 e0a6 e0a5 e0a4 e0a3 e0a2 e0a1 e0a0 2bh eq0-efficient 1 e0a15 e0a14 e0a 13 e0a12 e0a11 e0a10 e0a9 e0a8 2ch eq0-efficient 2 e0b7 e0b6 e0b5 e0b4 e0b3 e0b2 e0b1 e0b0 2dh eq0-efficient 3 0 0 e0b13 e0b12 e0b11 e0b10 e0b9 e0b8 2eh eq0-efficient 4 e0c7 e0c6 e0c5 e0c4 e0c3 e0c2 e0c1 e0c0 2fh eq0-efficient 5 e0c15 e0c14 e0c13 e0c12 e0c11 e0c10 e0c9 e0c8
[AK4955] ms1343-e-00 2011/12 - 82 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 31h check sum sum7 sum6 sum5 sum4 sum3 sum2 sum1 sum0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1 a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2 a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3 a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4 a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 note 54. pdn pin = ?l? resets the registers to their default values. note 55. the bits defined as 0 must contain a ?0? value. note 56. address 0eh and 31h are read only registers. writi ng access to these addresses is ignored and does not effect the operation.
[AK4955] ms1343-e-00 2011/12 - 83 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power management 1 pmpfil pmvcm pmdsp pmspk pmlo pmdac pmadr pmadl r/w r/w r/w r/w r/w r/ w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmadl: adc lch power management 0: power-down (default) 1: power-up pmadr: adc rch power management 0: power down (default) 1: power up when the pmadl or pmadr bit is changed from ?0 ? to ?1?, the initialization cycle (1059/fs=21.3ms @48khz, adrst1-0 bits = ?00?) starts. after in itializing, digital data of the adc is output. pmdac: dac power management 0: power-down (default) 1: power-up pmlo: stereo line output power management 0: power-down (default) 1: power-up pmspk: speaker-amp power management 0: power-down (default) 1: power-up pmdsp: dsp power management 0: power-down (default) 1: power-up pmvcm: vcom and regulator (2.3v) power management 0: power down (default) 1: power up pmpfil: programmable filter block (lpf/fil3/eq/5 band eq/alc) power management 0: power down (default) 1: power up the AK4955 can be powered-down by writing ?0? to the address ?00h? and pmpll, pmmicl/r, pmmp, pmbpg, pmdml/r, dmpe, pmv, pmcp and mcko bits. in this case, register values are maintained.
[AK4955] ms1343-e-00 2011/12 - 84 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h power management 2 sppsn dspstbn pmbpg pmbp m/s sumrstn mcko pmpll r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmpll: pll power management 0: ext mode and power down (default) 1: pll mode and power up mcko: master clock output enable 0: disable: mcko pin = ?l? (default) 1: enable: output frequency is selected by ps1-0 bits. sumrstn: reset bit for checksum 0: reset the checksum va lue to all ?0?. (default) 1: checksum reset release. m/s: master / slave mode select 0: slave mode (default) 1: master mode pmbp: mono input power management 0: power down (default) 1: power up stereo lineout and speaker path settings from the min pin can be set by beepl bit and beeps bit, respectively. pmbpg: beep generator power management 0: power down (default) 1: power up dspstbn: dsp clock control 0: clock stop (default) 1: clock supply program downloading is available when dspstbn bit = ?1? sppsn: speaker-amp power-save mode 0: power save mode (default) 1: normal operation when sppsn bit is ?0?, speaker-amp is in power-save mode. in this mode, the spp pin goes to hi-z and the spn pin outputs svdd/2 voltage. when pmspk bit = ?1?, sppsn b it is enabled. after the pdn pin is set to ?l?, speaker-amp is in power-down mode since pmspk bit is ?0?.
[AK4955] ms1343-e-00 2011/12 - 85 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h mic gain control 1 pmmicr pmmicl pmmp micl mgain3 mgain2 mgain1 mgain0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 1 1 0 mgain3-0: mic-amp gain control ( table 21 ) micl: mic power output voltage select 0: typ 2.5 v (avdd= 2.9~3.6v) (default) 1: typ 2.0v (avdd= 2.7~3.6v) pmmp: mic power management 0: power down (default) 1: power up pmmicl: mic-amp lch power management 0: power down (default) 1: power up pmmicr: mic-amp rch power management 0: power down (default) 1: power up addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h signal select 2 spkg1 spkg0 beeps dacs 0 0 inr inl r/w r/w r/w r/w r/w r r r/w r/w default 0 0 0 0 0 0 0 0 inl: adc lch input source select 0: lin1 pin (default) 1: lin2 pin inr: adc rch input source select 0: rin1 pin (default) 1: rin2 pin dacs: signal switch control from dac to speaker-amp 0: off (default) 1: on when dacs bit is ?1?, dac output signal is input to speaker-amp. beeps: signal switch control from the min pin to speaker-amp 0: off (default) 1: on spkg1-0: speaker-amp output gain select ( table 60 )
[AK4955] ms1343-e-00 2011/12 - 86 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h signal select 3 mono1 mono0 lops dacl beepl 0 lvcm1 lvcm0 r/w r/w r/w r/w r/ w r/w r r/w r/w default 0 0 0 0 0 0 0 1 lvcm1-0: stereo line output gain and common voltage setting ( table 58 ) beepl: signal switch control from the min pin to lineout 0: off (default) 1: on dacl: dac output signal to stereo line amp control 0: off (default) 1: on when pmlo bit = ?1?, this bit setting is enabled. lout and rout pins output vss1 when pmlo bit = ?0?. lops: stereo line output power save 0: normal operation (default) 1: power save mode mono1-0: lout/rout output signal mode select ( table 59 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h mode control 1 pll3 pll2 pll1 pll0 bcko 0 dif1 dif0 r/w r/w r/w r/w r/ w r/w r r/w r/w default 1 1 0 0 0 0 1 0 dif1-0: audio interface format ( table 17 ) default: ?10? (msb justified) bcko: master mode bick output frequency setting ( table 15 ) pll3-0: pll reference clock select ( table 4 ) default: ?1100? addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h mode control 2 ps1 ps0 ffte dspc fs3 fs2 fs1 fs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 fs3-0: sampling frequency ( table 5 , table 6 ) and mcki frequency setting ( table 11 ) these bits control sampling frequency in p ll mode, and mcki frequency in ext mode. dspc: dsp clock select 0: 256fs (default) 1: 512fs ffte: fft, ifft circuit power management 0: power down (default) 1: power up ps1-0: mcko frequency setting ( table 9 ) default: ?00? (256fs)
[AK4955] ms1343-e-00 2011/12 - 87 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h mode control 3 read thde t smute dvolc ovolc ivolc dem1 dem0 r/w r/w r r/w r/w r/w r/w r/w r/w default 0 0 0 1 1 1 0 1 dem1-0: de-emphasis control ( table 39 ) default: ?01? (off) ivolc: ivol control 0: independent 1: dependent (default) when ivolc bit = ?1?, ivl7-0 bits control both lch and rch volume levels, while register values of ivl7-0 bits are not written to ivr7-0 bits. ovolc: output digital volu me control mode select 0: independent 1: dependent (default) when ovolc bit = ?1?, ovl7-0 bits control both lch and rch volume levels, while register values of ovl7-0 bits are not written to ovr7-0 bits. dvolc: output digital volu me2 control mode select 0: independent 1: dependent (default) when dvolc bit = ?1?, dvl7-0 bits control both lch and rch volume levels, while register values of dvl7-0 bits are not written to dvr7-0 bits. smute: soft mute control 0: normal operation (default) 1: dac outputs soft-muted thdet: thermal shutdown detection 0: thermal shutdown off (default) 1: thermal shutdown on read: read function enable 0: disable (default) 1: enable
[AK4955] ms1343-e-00 2011/12 - 88 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h digital mic 0 0 pmdmr pmdml dclke 0 dclkp dmic r/w r r r/w r/w r/w r r/w r/w default 0 0 0 0 0 0 0 0 dmic: digital microphone connection select 0: analog microphone (default) 1: digital microphone dclkp: data latching edge select 0: lch data is latched on the dmclk rising edge (? ?). (default) 1: lch data is latched on the dmclk falling edge (? ?). dclke: dmclk pin output clock control 0: ?l? output (default) 1: 64fs output pmdml/r: input signal select with digital microphone ( table 20 ) default: ?00? adc digital block is powered-down by pmdml = pmdmr bits = ?0? when selecting a digital microphone input (dmic bit = ?1?). addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h timer select adrst1 adrst0 0 0 0 0 0 dvtm r/w r/w r/w r r r r r r/w default 0 0 0 0 0 0 0 0 dvtm: digital volume soft transition time setting ( table 42 ) default: ?0? (1024/fs) this transition time is for when dvl7-0 bits or dvr7-0bits are changed from 00h to ffh. adrst1-0: adc initial cycle setting ( table 16 ) default: ?00? (1059/fs)
[AK4955] ms1343-e-00 2011/12 - 89 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah alc timer select frn ztm1 ztm0 wtm2 wtm1 wtm0 rfst1 rfst0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 rfst1-0: alc first recovery speed ( table 34 ) default: ?01? (quad speed) wtm2-0: alc recovery waiting period ( table 30 ) default: ?000? (128/fs). a period of recovery operation when any limite r operation does not occur during alc operation ztm1-0: alc zero cross timeout setting ( table 29 ) default: ?000? (128/fs). in case of the p write operation or alc recovery operation, the volume is changed at zero crossing or timeout. frn: alc first recovery function enable 0: enable (default) 1: disable addr register name d7 d6 d5 d4 d3 d2 d1 d0 0bh alc mode control 1 lfst alc2 alc1 zelmn lmat1 lmat0 lmth1 lmth0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 lmth1-0: alc limiter detection level / recovery counter reset level ( table 27 ) default: ?00? lmat1-0: alc limiter att step ( table 28 ) default: ?00? zelmn: zero crossing detection en able at alc limiter operation 0: enable (default) 1: disable alc1: alc enable for recording 0: recording alc disable (default) 1: recording alc enable alc2: alc enable for playback 0: playback alc disable (default) 1: playback alc enable lfst: alc limiter operation when the out put level exceed fs(full-scale) level. 0: the volume is changed at zero crossing or zero crossing time out. (default) 1: when output of alc is larger than fs, ovol value is changed immediately (1/fs).
[AK4955] ms1343-e-00 2011/12 - 90 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ch alc mode control 2 iref7 iref6 iref5 iref4 iref3 iref2 iref1 iref0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 0 0 0 0 1 iref7-0: reference value of alc recovery operation (recording). 0.375db step, 242 level ( table 32 ) default: ?e1h? (+30.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh alc mode control 3 rgain1 rgain0 oref5 oref4 oref3 oref2 oref1 oref0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 1 0 1 0 0 0 oref7-0: reference value of alc recovery operation (playback). 0.375db step, 50 level ( table 33 ) default: ?28h? (+6.0db) rgain1-0: alc recovery gain step ( table 31 ) default: ?00? addr register name d7 d6 d5 d4 d3 d2 d1 d0 0eh alc volume vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 r/w r r r r r r r r default 1 0 0 1 0 0 0 1 vol7-0: current alc volume value, 0.375db step, 242 level, read operation only ( table 35 ) addr register name d7 d6 d5 d4 d3 d2 d1 d0 0fh lch input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 10h rch input volume control ivr7 ivr6 ivr5 ivr4 ivr3 ivr2 ivr1 ivr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 0 0 0 0 1 ivl7-0, ivr7-0: input digital volume, 0.375db step, 242 level ( table 38 ) default: ?e1h? (+30db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h lch output volume control ovl7 ovl6 ovl5 ovl4 ovl3 ovl2 ovl1 ovl0 12h rch output volume control ovr7 ovr6 ovr5 ovr4 ovr3 ovr2 ovr1 ovr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 1 0 0 0 1 ovl7-0, ovr7-0: output digital volume ( table 40 ) default: ?91h? (0db)
[AK4955] ms1343-e-00 2011/12 - 91 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 13h lch digital volume control dvol7 dvol6 dvol5 dvol4 dvol3 dvol2 dvol1 dvol0 14h rch digital volume control dvor7 dvor6 dvor5 dvor4 dvor3 dvor2 dvor1 dvor0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 1 1 0 0 0 dvol7-0, dvr7-0: output digital volume 2 ( table 41 ) default: ?18h? (0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 15h beep control bpcnt bpvcm bpm1 bpm0 0 0 bpfr1 bpfr0 r/w r/w r/w r/w r/w r r r/w r/w default 0 0 0 0 0 0 0 0 bpfr1-0: beep output frequency setting ( table 48 , table 49 ) default: ?00h? bpm1-0 bits: beep mode select ( table 43 ) default: ?00? internal resistance mode bpvcm: common voltage select of min input amp 0: typ. 1.15v (default) 1: typ. 1.65v bpcnt: beep output mode select 0: discontinuous output mode: beep is output for the number of times that is set by bptm6-0 bits. (default) 1: continuous output mode: beep is output while bpcnt bit = ?1?. addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h beep on time bpon7 bpon6 bpon5 bpon4 bpon3 bpon2 bpon1 bpon0 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bpon7-0: beep output on time setting ( table 51 , table 52 ) default: ?00h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 17h beep off time bpoff7 bpoff6 bpoff5 bpoff4 bpoff3 bpoff2 bpoff1 bpoff0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bpoff7-0: beep output off time setting ( table 53 , table 54 ) default: ?00h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 18h beep repeat count 0 bptm6 b ptm5 bptm4 bptm3 bptm2 bptm1 bptm0 r/w r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bptm6-0: beep repeat time setting ( table 55 ) default: ?00h?
[AK4955] ms1343-e-00 2011/12 - 92 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 19h beep volume control bpout 0 0 0 bplvl3 bplvl2 bplvl1 bplvl0 r/w r/w r r r r/ w r/w r/w r/w default 0 0 0 0 0 0 0 0 bplvl3-0: beep output level setting ( table 56 ) default: ?0h? (0db) bpout: beep output on/off control 0: off (default) 1: on beep is output for the number of times, that is selected by bptm6-0 bits, by setting bpout bit = ?1? while bpcnt bit = ?0?. bpout bit is automatically set to ?0? when beep output is finished. addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ah video control 0 0 0 0 vg1 vg0 pmcp pmv r/w r r r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 pmv: video block power management 0: power down (default) 1: power up pmcp: charge pump block power management 0: power down (default) 1: power up vg1-0: video amplifier gain select vg1-0 bits gain 00 +6db (default) 01 +9db 10 +12db 11 +16.5db table 63. video signal gain setting addr register name d7 d6 d5 d4 d3 d2 d1 d0 1bh hpf filter control 0 0 0 0 0 hpfc1 hpfc0 hpfad r/w r r r r r r/w r/w r/w default 0 0 0 0 0 0 0 1 hpfad: hpf1 control of adc 0: off 1: on (default) when hpfad bit is ?1?, the settings of hpfc1-0 bits are enabled. when hpfad bit is ?0?, hpfad block is through (0db). when pmadl bit = ?1? or pmadr b it = ?1?, set hpfad bit to ?1?. hpfc1-0: cut-off frequency setting of hpf1 (adc) ( table 25 ) default: ?00? (3.7hz @ fs = 48khz)
[AK4955] ms1343-e-00 2011/12 - 93 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ch digital filter select 1 0 0 lpf hpf eq0 gn1 gn0 fil3 r/w r r r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 1 fil3: stereo emphasis filter control 0: off 1: on (default) when fil3 bit = ?1?, settings of f3a13-0 and f3b13-0 bits are enabled. gn1-0: gain block gain setting ( table 26) default: ?00? (0db) eq0: gain correction filter (eq0) control 0: off (default) 1: on when eq0 bit = ?1?, settings of e0a15-0, e0b13-0 and e0c15-0 bits are enabled. when eq0 bit = ?0?, the audio data passes this block by 0db gain. hpf: hpf3 coefficient setting enable 0: off (default) 1: on when hpf bit is ?1?, settings of f1a13-0 and f1b13-0 b its are enabled. when hpf b it is ?0?, the audio data passes this block by 0db gain. lpf: lpf coefficient setting enable 0: off (default) 1: on when lpf bit is ?1?, settings of f2a13-0 and f2b13-0 b its are enabled. when lpf b it is ?0?, the audio data passes this block by 0db gain. addr register name d7 d6 d5 d4 d3 d2 d1 d0 1dh digital filter control 0 0 0 0 dspbp pfdac adcpf pfsdo r/w r r r r r/w r/w r/w r/w default 0 0 0 0 0 0 1 1 pfsdo: sdto output signal select 0: adc (+ 1st hpf) output 1: programmable filter / alc output (default) adcpf: programmable filter / alc input signal select 0: sdti 1: adc output (default) pfdac: dac input signal select 0: sdti (default) 1: programmable filter / alc output dspbp: dsp bypass mode enable 0: disable (default) 1: enable dsp block is bypassed.
[AK4955] ms1343-e-00 2011/12 - 94 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 1eh hpf2 co-efficient 0 f1a7 f1a6 f1a5 f1a4 f1a3 f1a2 f1a1 f1a0 1fh hpf2 co-efficient 1 0 0 f1a13 f1a12 f1a11 f1a10 f1a9 f1a8 20h hpf2 co-efficient 2 f1b7 f1b6 f1b5 f1b4 f1b3 f1b2 f1b1 f1b0 21h hpf2 co-efficient 3 0 0 f1b13 f1b12 f1b11 f1b10 f1b9 f1b8 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default f1a13-0 bits = 0x1fb0, f1b13-0 bits = 0x209f f1a13-0, f1b13-0: hpf3 coefficient (14bit x 2) default: f1a13-0 bits = 0x1fb0, f1b13-0 bits = 0x209f fc = 150hz@fs=48khz addr register name d7 d6 d5 d4 d3 d2 d1 d0 22h lpf co-efficient 0 f2a7 f2a6 f2a5 f2a4 f2a3 f2a2 f2a1 f2a0 23h lpf co-efficient 1 0 0 f2a13 f2a12 f2a11 f2a10 f2a9 f2a8 24h lpf co-efficient 2 f2b7 f2b6 f2b5 f2b4 f2b3 f2b2 f2b1 f2b0 25h lpf co-efficient 3 0 0 f2b13 f2b12 f2b11 f2b10 f2b9 f2b8 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 f2a13-0, f2b13-0: lpf coefficient (14bit x 2) default: ?0000h? addr register name d7 d6 d5 d4 d3 d2 d1 d0 26h fil3 co-efficient 0 f3a7 f3a6 f3a5 f3a4 f3a3 f3a2 f3a1 f3a0 27h fil3 co-efficient 1 f3as 0 f3a13 f3a12 f3a11 f3a10 f3a9 f3a8 28h fil3 co-efficient 2 f3b7 f3b6 f3b5 f3b4 f3b3 f3b2 f3b1 f3b0 29h fil3 co-efficient 3 0 0 f3b13 f3b12 f3b11 f3b10 f3b9 f3b8 2ah eq0-efficient 0 e0a7 e0a6 e0a5 e0a4 e0a3 e0a2 e0a1 e0a0 2bh eq0-efficient 1 e0a15 e0a14 e0a13 e0a12 e0a11 e0a10 e0a9 e0a8 2ch eq0-efficient 2 e0b7 e0b6 e0b5 e0b4 e0b3 e0b2 e0b1 e0b0 2dh eq0-efficient 3 0 0 e0b13 e0b12 e0b11 e0b10 e0b9 e0b8 2eh eq0-efficient 4 e0c7 e0c6 e0c5 e0c4 e0c3 e0c2 e0c1 e0c0 2fh eq0-efficient 5 e0c15 e0c14 e0c13 e0c12 e0c11 e0c10 e0c9 e0c8 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 f3a13-0, f3b13-0: stereo emphasis fil3 coefficient (14bit x 2) default: ?0000h? f3as: stereo emphasis fil3 select 0: hpf (default) 1: lpf e0a15-0, e0b13-0, e0c15-c0: gain compensa tion filter coefficient (16bit x 2 + 14bit x 1) default: ?0000h?
[AK4955] ms1343-e-00 2011/12 - 95 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 30h digital filter select 2 0 0 0 eq5 eq4 eq3 eq2 eq1 r/w r r r r/w r/ w r/w r/w r/w default 0 0 0 0 0 0 0 0 eq1: equalizer 1 coefficient setting enable 0: disable (default) 1: enable when eq1 bit = ?1?, settings of e1a15-0, e1b15-0 and e1c15-0 bits are enabled. when eq1 bit = ?0?, the audio data passes this block by 0db gain. eq2: equalizer 2 coefficient setting enable 0: disable (default) 1: enable when eq2 bit = ?1?, settings of e2a15-0, e2b15-0 and e2c15-0 bits are enabled. when eq2 bit = ?0?, the audio data passes this block by 0db gain. eq3: equalizer 3 coefficient setting enable 0: disable (default) 1: enable when eq3 bit = ?1?, settings of e3a15-0, e3b15-0 and e3c15-0 bits are enabled. when eq3 bit = ?0?, the audio data passes this block by 0db gain. eq4: equalizer 4 coefficient setting enable 0: disable (default) 1: enable when eq4 bit = ?1?, settings of e4a15-0, e4b15-0 and e4c15-0 bits are enabled. when eq4 bit = ?0?, the audio data passes this block by 0db gain. eq5: equalizer 5 coefficient setting enable 0: disable (default) 1: enable when eq5 bit = ?1?, settings of e5a15-0, e5b15-0 and e5c15-0 bits are enabled. when eq5 bit = ?0?. the audio data passes this block by 0db gain. addr register name d7 d6 d5 d4 d3 d2 d1 d0 31h check sum sum7 sum6 sum5 sum4 sum3 sum2 sum1 sum0 r/w r r r r r r r r default 0 0 0 0 0 0 0 0 sum7-0: checksum read
[AK4955] ms1343-e-00 2011/12 - 96 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 32h e1 co-efficient 0 e1a7 e1a6 e1a5 e1a4 e1a3 e1a2 e1a1 e1a0 33h e1 co-efficient 1 e1a15 e1a14 e1a13 e1a12 e1a11 e1a10 e1a9 e1a8 34h e1 co-efficient 2 e1b7 e1b6 e1b5 e1b4 e1b3 e1b2 e1b1 e1b0 35h e1 co-efficient 3 e1b15 e1b14 e1b13 e1b12 e1b11 e1b10 e1b9 e1b8 36h e1 co-efficient 4 e1c7 e1c6 e1c5 e1c4 e1c3 e1c2 e1c1 e1c0 37h e1 co-efficient 5 e1c15 e1c14 e1c13 e1c12 e1c11 e1c10 e1c9 e1c8 38h e2 co-efficient 0 e2a7 e2a6 e2a5 e2a4 e2a3 e2a2 e2a1 e2a0 39h e2 co-efficient 1 e2a15 e2a14 e2a13 e2a12 e2a11 e2a10 e2a9 e2a8 3ah e2 co-efficient 2 e2b7 e2b6 e2b5 e2b4 e2b3 e2b2 e2b1 e2b0 3bh e2 co-efficient 3 e2b15 e2b14 e2b13 e2b12 e2b11 e2b10 e2b9 e2b8 3ch e2 co-efficient 4 e2c7 e2c6 e2c5 e2c4 e2c3 e2c2 e2c1 e2c0 3dh e2 co-efficient 5 e2c15 e2c14 e2c13 e2c12 e2c11 e2c10 e2c9 e2c8 3eh e3 co-efficient 0 e3a7 e3a6 e3a5 e3a4 e3a3 e3a2 e3a1 e3a0 3fh e3 co-efficient 1 e3a15 e3a14 e3a13 e3a12 e3a11 e3a10 e3a9 e3a8 40h e3 co-efficient 2 e3b7 e3b6 e3b5 e3b4 e3b3 e3b2 e3b1 e3b0 41h e3 co-efficient 3 e3b15 e3b14 e3b13 e3b12 e3b11 e3b10 e3b9 e3b8 42h e3 co-efficient 4 e3c7 e3c6 e3c5 e3c4 e3c3 e3c2 e3c1 e3c0 43h e3 co-efficient 5 e3c15 e3c14 e3c13 e3c12 e3c11 e3c10 e3c9 e3c8 44h e4 co-efficient 0 e4a7 e4a6 e4a5 e4a4 e4a3 e4a2 e4a1 e4a0 45h e4 co-efficient 1 e4a15 e4a14 e4a13 e4a12 e4a11 e4a10 e4a9 e4a8 46h e4 co-efficient 2 e4b7 e4b6 e4b5 e4b4 e4b3 e4b2 e4b1 e4b0 47h e4 co-efficient 3 e4b15 e4b14 e4b13 e4b12 e4b11 e4b10 e4b9 e4b8 48h e4 co-efficient 4 e4c7 e4c6 e4c5 e4c4 e4c3 e4c2 e4c1 e4c0 49h e4 co-efficient 5 e4c15 e4c14 e4c13 e4c12 e4c11 e4c10 e4c9 e4c8 4ah e5 co-efficient 0 e5a7 e5a6 e5a5 e5a4 e5a3 e5a2 e5a1 e5a0 4bh e5 co-efficient 1 e5a15 e5a14 e5a13 e5a12 e5a11 e5a10 e5a9 e5a8 4ch e5 co-efficient 2 e5b7 e5b6 e5b5 e5b4 e5b3 e5b2 e5b1 e5b0 4dh e5 co-efficient 3 e5b15 e5b14 e5b13 e5b12 e5b11 e5b10 e5b9 e5b8 4eh e5 co-efficient 4 e5c7 e5c6 e5c5 e5c4 e5c3 e5c2 e5c1 e5c0 4fh e5 co-efficient 5 e5c15 e5c14 e5c13 e5c12 e5c11 e5c10 e5c9 e5c8 r/w r/w r/w r/w r/ w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 e1a15-0, e1b15-0, e1c15-0: equalizer 1 coefficient (16bit x3) default: ?0000h? e2a15-0, e2b15-0, e2c15-0: equalizer 2 coefficient (16bit x3) default: ?0000h? e3a15-0, e3b15-0, e3c15-0: equalizer 3 coefficient (16bit x3) default: ?0000h? e4a15-0, e4b15-0, e4c15-0: equalizer 4 coefficient (16bit x3) default: ?0000h? e5a15-0, e5b15-0, e5c15-0: equalizer 5 coefficient (16bit x3) default: ?0000h?
[AK4955] ms1343-e-00 2011/12 - 97 - system design figure 75 ~ figure 77 show the system connection diagram. an evaluation board (akd4955) is available for fast evaluation as well as suggestions for peripheral circuitry. digital ground a nalog ground digital 1.6 2.0v AK4955 analog 2.7 5.5v top view analog 2.7 3.6v 0.1u dvdd -0.2 or 1.6 ~ 3.6v 0.1u 0.1u 10u + analog 2.7 5.5v 2.2u 2.2u 10u + 0.1u 2.2u + 10u 0.1u vss2 dvdd lout bick lrck rout mcki sdti rin1 rin2 vss1 vcom lvdd spp vss3 lin1 svdd spn vin vss1 pvee i 2 c avdd vss1 lin2 mpwr regfil cclk csn pdn mcko cdtio vout sdto tvdd min digital figure 75. power supplies connection diagram notes: - vss1, vss2, and vss3 of the AK4955 must be distributed separately from the ground of external controllers.
[AK4955] ms1343-e-00 2011/12 - 98 - AK4955 top view vss2 dvdd lout bick lrck rout mcki sdti rin1 rin2 vss1 vcom lvdd spp vss3 lin1 svdd spn vin vss1 pvee i 2 c avdd vss1 lin2 mpwr regfil cclk csn pdn mcko cdtio vout sdto tvdd min dsp p digital ground a nalog ground figure 76. digital block connection diagram (3-wire serial mode; i2c pin = ?l?), note: - all digital input pins must not be allowed to float. - when the AK4955 is used in master mode, lrck and bi ck pins are floating before m/s bit is changed to ?1?. therefore, a pull-up or pull-down resistor around 100k must be connected to lrck and bick pins of the AK4955.
[AK4955] ms1343-e-00 2011/12 - 99 - digital ground a nalog ground AK4955 top view speaker internal mic external mic 75 vss2 dvdd lout bick lrck rout mcki sdti rin1 rin2 vss1 vcom lvdd spp vss3 lin1 svdd spn vin vss1 pvee i 2 c avdd vss1 lin2 mpwr regfil cclk csn pdn mcko cdtio vout sdto tvdd min 0.1u figure 77. audio and video input/output connection (external resistance mode; bpm1-0 bits = ?01?)
[AK4955] ms1343-e-00 2011/12 - 100 - 1. grounding and power supply decoupling the AK4955 requires careful attention to power suppl y and grounding arrangements. if avdd, dvdd, tvdd, svdd and lvdd are supplied separately, the power-up sequence is not critical. vss1, vss2, and vss3 of the AK4955 must be connected to the analog ground plane. system analog gr ound and digital ground should be wired separately and connected together as close as possible to where the supplies are brought onto the printed circuit board. decoupling capacitors must be as near to the AK4955 as possible, with the small value ceramic capacitor being the nearest. 2. internal regulated voltage power supply vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vss1 pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the AK4955. 3. analog inputs the mic and line inputs supports single-ended. the input signa l range scales with nominally at typ. 2.07vpp (@ mgain = 0db), centered around the internal signal ground (typ. 1.15v). usually the input signal is ac coupled with a capacitor. the cut-off frequency is fc = 1/(2 rc). the AK4955 can accept input voltages from vss1 to avdd. 6. analog outputs the input data format for the dac is 2?s complement. th e output voltage is a positive full scale for 7fffffh (@24bit) and a negative full scale for 800000h (@24bit). the ideal output is vcom voltage for 000000h (@24bit data). the common voltage of stereo lineout is typ. 2.52vpp centered on 1.5v (typ) (lvcm1-0 bits = ?01?). the speaker outputs are centered on svdd/2 (typ).
[AK4955] ms1343-e-00 2011/12 - 101 - control sequence clock set up when any circuits of the AK4955 are powered-up, the clocks must be supplied. 1. pll master mode bick pin lrck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) 10msec(max) output (1) (7) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input m/s bit (addr:01h, d3) mcko pin output (9) (8) 10msec(max) 1.0mses(max) (6) example: audio i/f format: msb justified (adc & dac) bick frequency at master mode: 64fs input master clock select at pll mode: 13.5mhz mcko: enable sampling frequency: 48khz (1) power supply & pdn pin = ?l? ? ?h? ( 3 ) addr:00h, data:40h (2)dummy command addr:01h, data:08h addr:05h, data:aah addr:06h, data:0bh ( 4 ) addr:01h, data:0bh mcko, bick and lrck output figure 78. clock set up sequence (1) < example > (1) after power up, pdn pin ?l? ?h?. ?l? time of 180ns or more is needed to reset the AK4955. (2) after dummy command input, m/s, dif1-0, bcko, pll3-0, fs3-0 and ps1-0 bits must be set during this period. (3) power up vcom and regulator: pmvcm bit = ?0? ?1? vcom and regulator must first be powered-up before the other block operates. power up time is 0.4ms (typ) and 1.0ms (max) when both capacitances of an extern al capacitor for the vcom and regfil pins are 2.2 f. (4) in case of using mcko output: mcko bit = ?1? in case of not using mcko output: mcko bit = ?0? (5) pll starts after pmpll bit changes from ?0? to ?1? and mcki is supplie d from an external source, and pll lock time is 10ms (max). (6) bick pin outputs ?h? and lrck pin outputs ?l? during this period. (7) the AK4955 starts to output the lrck and bick clocks after the pll became stable. then normal operation starts. (8) an invalid frequency is output from the mcko pin during this period if mcko bit = ?1?. (9) a normal clock is output from the mcko pin after the pll is locked if mcko bit = ?1?.
[AK4955] ms1343-e-00 2011/12 - 102 - 2. pll slave mode (bick pin) pmpll bit (addr:01h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) bick pin (4) (5) input 1.0mses(max) 4fs of example: audio i/f format: msb justified (adc & dac) pll reference clock: bi ck bick frequency: 64fs sampling frequency: 48khz (1) power supply & pdn pin = ?l? ? ?h? ( 3 ) addr:00h, data:40h (2) dummy command addr:05h, data:32h addr:06h, data:02h (4) addr:01h, data:01h figure 79. clock set up sequence (2) (1) after power up: pdn pin ?l? ?h? ?l? time of 180ns or more is needed to reset the AK4955. (2) after dummy command input, dif1-0, pll3-0, and fs3-0 bits must be set during this period. (3) power up vcom and regulator: pmvcm bit = ?0? ?1? vcom and regulator must first be powered-up before the other block operates. power up time is 0.4ms (typ) and 1.0ms (max) when both capacitances of an extern al capacitor for the vcom and regfil pins are 2.2 f. (4) pll starts after the pmpll bit change s from ?0? to ?1? and pll reference clock (bick pin) is supplied. pll lock time is 2ms (max) when bick is a pll reference clock. (5) normal operation stats after that the pll is locked.
[AK4955] ms1343-e-00 2011/12 - 103 - 3. pll slave mode (mcki pin) bick pin lrck pin mcko bit (addr:01h, d1) pmpll bit (addr:01h, d0) (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) mcki pin (5) (4) input mcko pin output (6) (7) 10msec(max) (8) input 1.0mses(max) example: audio i/f format: msb justified (adc & dac) input master clock select at pll mode: 13.5mhz mcko: enable sampling frequency: 48khz (1) power supply & pdn pin = ?l? ? ?h? ( 3 ) addr:00h, data:40h (2)dummy command addr:05h, data:aah addr:06h, data:0bh ( 4 ) addr:01h, data:03h mcko output start bick and lrck input start figure 80. clock set up sequence (3) (1) after power up: pdn pin ?l? ?h? ?l? time of 180ns or more is needed to reset the AK4955. (2) after dummy command input, dif1-0, pll3-0, fs3-0 and ps1-0 bits must be set during this period. (3) power up vcom and regulator: pmvcm bit = ?0? ?1? vcom and regulator must first be powered-up before the other block operates. power up time is 0.4ms (typ) and 1.0ms (max) when both capacitances of an extern al capacitor for the vcom and regfil pins are 2.2 f. (4) enable mcko output: mcko bit = ?1? (5) pll starts after that the pmpll b it changes from ?0? to ?1? and pll reference clock (mcki pin) is supplied. pll lock time is 10ms (max). (6) a normal clock is output from mcko after pll is locked. (7) an invalid frequency is output from mcko during this period. (8) bick and lrck clocks must be synchronized with mcko clock.
[AK4955] ms1343-e-00 2011/12 - 104 - 4. ext slave mode (1) power supply pdn pin pmvcm bit (addr:00h, d6) (2) (3) lrck pin bick pin (4) input (4) mcki pin input example: audio i/f format : msb jusified (adc and d ac) input mcki frequency: 256fs sampling frequency: 48khz (1) power supply & pdn pin = ? l? ? ?h? ( 3 ) addr:00h, data:40h (2)dummy command addr:05h, data:02h addr:06h, data:02h mcki, bick and lrck input figure 81. clock set up sequence (4) (1) after power up: pdn pin ?l? ?h? ?l? time of 180ns or more is needed to reset the AK4955. (2) after dummy command input, dif1-0 and fs3-0 bits must be set during this period. (3) power up vcom and regulator: pmvcm bit = ?0? ?1? vcom and regulator must first be powered-up before the other block operates. power up time is 0.4ms (typ) and 1.0ms (max) when both capacitances of an extern al capacitor for the vcom and regfil pins are 2.2 f. (4) normal operation starts after the mcki, lrck and bick are supplied.
[AK4955] ms1343-e-00 2011/12 - 105 - 5. ext master mode (1) power supply pdn pin pmvcm bit (addr:00h, d6) (4) (5) lrck pin bick pin (3) mcki pin input m/s bit (addr:01h, d3) output (2) example: audio i/f format: msb justified (adc and dac) input mcki frequency: 256fs sampling frequency: 48khz bc ko: 6 4fs (1) power supply & pdn pin = ?l? ? ?h? ( 5 ) addr:00h, data:40h (4)addr:05h, data:0ah addr:06h, data:02h addr:01h, data:08h bick and lrck output (3) mcki input (2) dummy command figure 82. clock set up sequence (5) (1) after power up: pdn pin ?l? ?h? ?l? time of 180ns or more is needed to reset the AK4955. (2) dummy command must be input during this period. (3) mcki is supplied. (4) after dif1-0, bcko and fs3-0 bits are set. m/s bit should be set to ?1?. then lrck and bick are output. (5) power up vcom and regulator: pmvcm bit = ?0? ?1? vcom and regulator must first be powered-up before the other block operates. power up time is 0.4ms (typ) and 1.0ms (max) when both capacitances of an extern al capacitor for the vcom and regfil pins are 2.2 f.
[AK4955] ms1343-e-00 2011/12 - 106 - dsp block (2) addr: 01h, d7: dspstabn bit = ?1? ram clear period (3) addr: 1dh, d7: pmdsp bit = ?1? dsp program start (1) addr: 06h, d3-0: data: 0bh example pll mode sampling frequency: 48khz figure 83. dsp sequence at first, clocks should be supplied according to ? clock set up ? sequence. (1) in pll mode, access the dsp with an interval of p ll lock time (max. 10ms) after changing the sampling frequency. (2) start program download period (addr = 01h, d6 dspstbn bit = ?1?). write a program to pram and data to cram during this period. there is no limit for the program download period. (3) power-up the dsp (addr = 00h, d5 pmdsp bit = ?1?). dram initialization starts when power-up the dsp after downloading a program. dram initialization cycle is set by dspc bit; max. 11lrck 230 s when dspc bit = ?0? (dsp: 256fs operation) and max. 6lrck 125 s when dspc bit = ?1? (dsp: 512fs operation). dram initialization cycle (23 0 s @ dspc bit =?0? 125 s @ dspc bit =?1?) dsp program operation start dsp start dsp program download period (1) (3) fs3-0 bits (addr: 06h, d3-0) (2) 0000 xxxx dspstbn bit (addr: 01h, d6) pmdsp bit (addr: 00h, d5) pll mode max .10ms
[AK4955] ms1343-e-00 2011/12 - 107 - mic input recording (stereo) example: pl l master m ode audio i/f format: msb justified pre mic amp: +18db mic power 1 on sampling frequency: 48khz alc1 setting: refer to table 36 hpf1: fc=118.4hz, adrst1-0 bits = ?00? programmable filt er off (3) addr:09h, data:00h addr:0ah, data:71h ( 1 ) addr:06h, data:0bh ( 4 ) a ddr:0ch, data:e1h (5) addr:0fh, data:e1h ( 6 ) addr:0dh, data:00h (7) addr:0bh, data:a1h (8) addr:1dh, data:03h ( 9 ) addr:1bh, data:04h ( 10 ) addr:1bh, data:05h (11) addr:00h, data:c3h recordin g ( 13 ) addr:0bh, data:81h ( 2 ) addr:02h, data:e6h (12) addr:00h, data:40h figure 84. mic input recording sequence this sequence is an example of alc1 setting at fs=48kh z. for changing the parameter of alc, please refer to table 36 ?. at first, clocks should be supplie d according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bits). when the AK4955 is the pll mode, mic, adc and programmable filter of (11) must be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up mic amp and mic power. (addr = 02h) (3) set up alc1 timer, adrst1-0 bits (addr = 09h, 0ah) (4) set up iref value at alc1 (addtr = 0ch) (5) set up ivol value at alc1 operation start (addr = 0fh) (6) set up rgain1-0 bits (addr =0dh) (7) set up lmth1-0, lmat1-0, zelmn, al c1 and lfst bits (addr = 0bh) (8) set up programmable filter path: pfsdo bit = adcpf bit = ?1? (addr = 1dh) (9) set up coefficient programmable filter (addr: 1ch, 1eh ~ 25h, 32h ~ 4fh) (10) set up of programmable filter on/off (11) power up adc and programmable filter: pmadl =pmadr =pmpfil bits = ?0? ?1? the initialization cycle time of adc is 1059/fs=22ms @ fs=48khz, adrst1-0 bit = ?00?. adc outputs ?0? data during the initialization cycle. after the alc1 bit is set to ?1?, the alc1 operation starts from ivol value of (5). (12) power down adc and programmable filter: pmadl = pmadr = pmpfil bits = ?1? ?0? (13) alc disable: alc1 bit = ?1? ?0? fs3-0 bits (addr:06h, d3-0) pmpfil bit pmadl/r bit (addr:00h, d7, d1-0) sdto pin state 1011 0000 06h 0 data output normal data output (11) alc1 state alc1 enable alc1 disable (6) alc control 1 (addr:0bh) 00, 00h a1h (4) alc control 2 (addr:0ch ) 00 e1h ivl7-0 bits (addr:0fh) e1h 00, 70h (5) (8) digital filter path (addr:1dh) 03h 03h filter select (addr:1ch, 30h) xx....x (9) 0 data output (12) alc1 disable initialize 1059/fs (2) timer select (addr:09h, d7-6 addr:0ah) e6h (3) alc control 3 (addr:0dh, d7-6) 00h 00 (7) xx....x (1) filter co-ef (addr:1ch,1e-25h, 32-4fh) xx....x (10) xx....x mic control (addr:02h) e1h e1h (13) 00h
[AK4955] ms1343-e-00 2011/12 - 108 - digital mic input recording (stereo) fs3-0 bits (addr:06h, d3-0) pmpfil bit (addr:00h, d7) digital mic (addr:08h) sdto pin state 1011 0000 00, 00h 0 data output normal data ouput (10) alc1 state alc1 enable alc1 disable (6) alc control 1 (addr:0bh) 00h a1h (4) alc control 2 (addr:0ch ) 00 e1h ivl7-0 bits (addr:0fh) e1h e1h (5) (8) digital filter path (addr:1dh) 03h xxh filter co-ef (addr:1e-25h 32-4fh) xx....x xx....x filter select (addr:1ch, 30h) xx....x (9) 0 data output (11) (13) (12) alc1 disable 1059/fs (2) timer select (addr:09h, d7-6 addr:0ah,) 00, 70h (3) alc control 3 (addr:0dh, d7-6) 00h 00 (7) xx....x (1) 0011 x 0 xx 0000 x 0 xx 0000 x 0 xx (14) 00h example: pll mast er mode audio i/f format: msb justified sampling frequency: 48khz digital mic setting: d ata is latched on the dmclk failing edge alc1 setting: refer to table 35 hpf1: fc=118.4hz, adrst1-0 bits = ?00? prog ra mm able filte r off (2) addr:09h, data:00h addr:0ah, data:70h ( 1 ) a ddr:06h, data:0bh ( 3 ) addr:0ch, data:e1h (4) addr:0fh, data:e1h ( 5 ) addr:0dh, data:00h (6) addr:0bh, data:a1h (7) addr:1dh, data:03h (8) addr:1e ~ 25h, data:default addr 32 ~ 4fh, data: default ( 9 ) addr:1ch, data:00h (10) addr:00h, data:c0h ( 11 ) addr:08h, data:3bh recordin g ( 12 ) addr:08h, data:0bh ( 13 ) addr:00h, data:40h ( 14 ) addr:0bh, data:00h figure 85. digital mic input recording sequence this sequence is an example of alc1 setting at fs=48kh z. for changing the parameter of alc, please refer to table 36 . at first, clocks shoul d be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bits). when the AK4955 is pll mode, digital mic of (11) and programmable filter of (10) must be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up alc1 timer and adrst1-0 bits (addr = 09h, 0ah) (3) set up iref value for alc1 (addtr = 0ch) (4) set up ivol value at alc1 operation start (addr = 0fh) (5) set up rgain1-0 bits (addr =0dh) (6) set up lmth1-0, lmat1-0, zelmn, alc1, lfst bits (addr = 0bh) (7) set up programmable filter path: pfsdo bit = adcpf bit = ?1? (addr = 1dh) (8) set up coefficient of programmable filter (addr: 1eh ~ 25h, 32h ~ 4fh) (9) set up programmable filter on/off (10) power up programmable filter: pmpfil bit = ?0? ?1? (11) set up & power up digital mic: pmdmr = pmdml bits = ?0? ?1? the initialization cycle time of adc is 1059/fs=22ms @ fs=48khz, .adrst1-0 bit = ?00?. adc outputs ?0? data during initialization cycle. after the alc1 bit is set to ?1?, the alc1 operation starts from ivol value of (4). (12) power down digital mic: pmdmr =pmdml bits = ?1? ?0? (13) power down programmable filter: pmpfil bit = ?1? ?0? (14) alc1 disable: alc1 bit = ?1? ?0?
[AK4955] ms1343-e-00 2011/12 - 109 - speaker-amp output fs3-0 bits (addr:06h, d3-0) ovl/r7-0 bits (addr:11h&12h) pmpfil bit pmdac bit (addr:00h,d7&d2) pmspk bit (addr:00h, d4) 1011 0000 91h 91h spp pin normal output sppsn bit (addr:02h, d7) hi-z hi-z spn pin normal output hi-z hi-z svdd/2 svdd/2 (1) (7) c1h 00h (5) alc control 1 (addr:0bh) (8) (9) (12) (10) dacs bit (addr:03h, d4) (11) 10 00 (3) spkg1-0 bits (addr:03h, d7-6) (2) (4) timer select (addr:0ah) 00h 70h alc control 3 (addr:0dh) 28h 28h digital filter path (addr:1dh) 03h 04h (6) alc2 enable alc2 disable alc2 state alc2 disable > 1 ms example: pll master mode audio i/f format: msb justified sampling frequency:48khz spkgain = +12.1db digital volume: 0db alc2: enable programmable filter off (2) addr:03h, data:90h (5) addr:0bh, data:c1h (1) addr:06h, data:0bh (6) addr:11h & 12h, data:91h (8) addr:00h, data:d4h (9) addr:02h, data:a3h (10) addr:02h, data:23h playback (11) addr:02h, data:03h (12) addr:00h, data:40h addr:03h, data:40h (4) addr:0dh, data:28h (7) addr:1dh, data:04h (3) addr:0ah, data:70h figure 86. speaker-amp output sequence at first, clocks must be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bits). when th e AK4955 is pll mode, dac and speaker-amp of (9) must be powered-up in consideration of pll lo ck time after a sampling frequency is changed. (2) set up the path of dac spk-amp: dacs bit = ?0? ?1? spk-amp gain setting: spkg1-0 bits = ?00? ?01? (3) set up timer select for alc2 (addr = 0ah) (4) set up oref value for alc2 and rgain1-0 bits (addr = 0dh) (5) set up lmth1-0, lmat1-0, zelmin, al c2 and lfst bits (addr = 0bh) (6) set up the output digital volume (addr = 11h, 12h) set up ovol value at alc2 operation start. when ovolc bit is ?1? (default), ovl7- 0 bits set the volume of both channels. when alc2 bit = ?0?, it could be digital volume control. (7) set up programmable filter path: pfdac, adcpf, pfsdo bits (addr = 1dh) (8) power up dac, programmable filter and speaker: pmdac = pmpfil = pmspk bits = ?0? ?1? (9) exit the power-save-mode of speaker-amp: sppsn bit = ?0? ?1? (10) enter speaker-amp power-s ave-mode: sppsn bit = ?1? ?0? (11) disable the path of ?dac spk-amp?: dacs bit = ?1? ?0? (12) power down dac, programmable filter and speaker: pmdac = pmpfil = pmspk bits = ?1? ?0?
[AK4955] ms1343-e-00 2011/12 - 110 - beep signal output from speaker-amp pmspk bit (addr:00h, d4) beep gen bits (addr:15-19h) sppsn bit (addr:01h, d7) (1) (2) (3) pmbp bit (addr:01h, d4) (7) xxh yyh (6) bpout bit (addr:19h, d7) (5) beep output hi-z hi-z beep output hi-z hi-z svdd/2 svdd/2 spp pin spn pin > 1 ms svdd/2 svdd/2 (4) (8) x0 1 0 example:default (2) addr:00h, data:50h (1) addr:15-19h, data:yyh addr:19h,d7, bpout bit =?0? (3) addr:01h, data:20h beep signal output (5) addr:19h, data:80h addr:19h, data:00h (auto) (8) addr:00h, data:40h (6) addr:01h, data:20h (4) addr:01h, data:a0h (7) addr:01h, data:00h figure 87. ?beep generator speaker-amp? output sequence at first, clocks must be supplied according to ?clock set up? sequence. when the AK4955 is pll mode, speaker-amp of (2) and beep generator of (3) must be powered-up in consideration of pll lock time after a sampling frequency is changed. (1) set up beep generator (addr: 15h ~ 19h) (bpout bit must be set to ?0?.) (2) power up speaker: pmspk bit = ?0? ?1? (3) power up beep generator: pmbp bit = ?0? ?1? (4) exit the power-save-mode of speaker-amp: sppsn bit = ?0? ?1? (5) beep output: bpout bit= ?0? ?1? after outputting data determined set times, bpout bit automatically returns to ?0?. (6) enter speaker-amp power-s ave-mode: sppsn bit = ?1? ?0? (7) power down beep generator: pmbp bit = ?1? ?0? (8) power down speaker: pmspk bit = ?1? ?0?
[AK4955] ms1343-e-00 2011/12 - 111 - stereo line output dvl7-0 bits (addr:13, 14h) pmdac bit (addr:00h, d18) pmlo bit (addr:00h, d19) xxh 18h lout pin rout pin (1) (4) normal output (6) (5) >300 ms (7) (8) >300 ms lops bit (addr:04h, d5) dacl bit (addr:04h, d16) digital filter path (addr:1dh) 00h (2) xxh lvcm1-0 bits (addr:04h, d1-0) (3) xx 01 example: digital volume 2: 0db lcvm1-0 bis: 0db program ma ble filter off (1) addr:13, 14h, data:18h (2) addr:1dh, data:00h (4) addr:00h, data:0ch (5) addr:04h, data:11h playback (6) addr:04h, data:31h (7) addr:00h, data:00h (8) addr:04h, data:11h (3) addr:04h, data:31h figure 88. stereo lineout sequence at first, clocks should be supplied according to ?clock set up? sequence. (1) set up output digital volume 2 (addr = 13, 14h) (2) set up programmable filter path (pfdac , adcpf and pfsdo bits). (addr = 1dh) (3) set up the path of ?dac stereo lime-amp?: dacl bit = ?0? ?1? (addr = 04h) set up the stereo line amplifier: lvcm1-0 bits = ?xx? ?01? set the stereo line amplifier to power save mode. lops bit = ?0? ?1? (4) power up stereo line-amp: pmdac = pmlo bits = ?0? ?1? (addr = 00h) lout and rout pins rise up to vcom voltage after pm lo bit is changed to ?1?. rise time to 99% vcom voltage is 300ms(max.) when c=1 f and r l =10k . (5) exit power-save mode of st ereo line-amp: lops bit = ?1? ?0? (addr=04h) lops bit should be set to ?0? after lout and rout pi ns rise up. stereo line-amp goes to normal operation by setting lops bit to ?0?. (6) enter power save mode of stereo line-amp: lops bit = ?0? ?1? (addr = 04h) (7) power down dac and stereo line-amp: pmdac=pmlo= ?1? ?0?. (addr=00h) lout and rout pins fall down to 1% of the vcom voltage. fall time is 300ms (max.) at c=1 f and r l =10k . (8) disable the path of ?dac stereo line-amp?: dacl bit = ?1? ?0? (addr=04h) exit power-save mode of the st ereo-line amp: lops bit = ?1? ?0? lops bit should be set to ?0? after lout and rout pins fall down.
[AK4955] ms1343-e-00 2011/12 - 112 - video input/output example: audio function :no use video gain = +6db (2) addr:1ah, data:03h video out p ut (3) addr:1ah, data:00h (1) addr:1ah, data:00h figure 89. video output sequence when only the video block is in operation, the clocks are not needed. (1) set up the video gain (vg1-0 bits). (2) power up video amp and charge pump: pmv, pmcp bits = ?0? ?1? (*) wait time is the time until the video clamp circuit output is stabled. it depends on the value of a dc cut capacitor for the vin pin and the dc offset voltage of a video signal. example) in case of the input capacitor of the vin pin is 0.1 f and the dc offset voltage is 150mv. wait time = (max) 180ms (3) power down video amp: pmv, pmcp bits = ?0? ?1? the vout pin output is stopped and becomes 0v. (2) vout pin vs s1 vs s 1 nor mal outp ut (1) vg1- 0 bi ts (addr: 1ah, d3-2) 00 xx clocks clocks can be sto pp ed , if on l y vide o o ut p ut is enabled. pmc p bit (addr: 1ah, d1) pmv bit (addr: 1ah, d0) 1 1 0 0 0 0 (3) wait tim e (*)
[AK4955] ms1343-e-00 2011/12 - 113 - stop of clock when any circuits of the AK4955 are powered-up, the clocks must be supplied. 1. pll master mode external mcki pmpll bit (addr:01h, d0) mcko bit (addr:01h, d1) input (3) (1) (2) "0" or "1" example: audio i/f format: msb justified (adc & dac ) bick frequency at master mode: 64fs input master clock select at pll mode: 12.288mhz ( 3 ) sto p an external mcki ( 1 ) ( 2 ) addr:01h, data:08h figure 90. clock stopping sequence (1) (1) power down pll: pmpll bit = ?1? ?0? (2) stop mcko clock: mcko bit = ?1? ?0? (3) stop an external master clock. 2. pll slave mode (bick pin) external bick pmpll bit (addr:01h, d0) input (1) (2) external lrck input (2) example audio i/f format : msb justified (adc & dac) pll reference clock: bick bick frequency: 64fs (1) addr:01h, data:00h (2) stop the external clocks figure 91. clock stopping sequence (2) (1) power down pll: pmpll bit = ?1? ?0? (2) stop the external bick and lrck clocks.
[AK4955] ms1343-e-00 2011/12 - 114 - 3. pll slave (mcki pin) external mcki pmpll bit (addr:01h, d0) input (1) (2) mcko bit (addr:01h, d1) (1) example audio i/f format: msb justified (adc & dac) pll reference clock: mcki bick frequency: 64fs (1) addr:01h, data:00h (2) stop the external clocks figure 92. clock stopping sequence (3) (1) power down pll: pmpll bit = ?1? ?0? stop mcko output: mcko bit = ?1? ?0? (2) stop the external master clock. 4. ext slave mode external lrck input (1) external bick input (1) external mcki input (1) example audio i/f format :msb justified(ad c & dac) input mcki frequency:256fs ( 1 ) sto p the external clocks figure 93. clock stopping sequence (4) (1) stop the external mcki, bick and lrck clocks. power down power supply current can not be shut down by stopping clocks and setting pmvcm bit = ?0?. power supply current can be shut down (typ. 1 a) by stopping clocks a nd setting the pdn pin = ?l?. when the pdn pin = ?l?, all registers are initialized.
[AK4955] ms1343-e-00 2011/12 - 115 - package 3.0160.03 a c b d e f 6 4 5 3 2 1 0.5 0.5 a 1 0.3850.028 0.2400.03 0.6250.058 c 0.075 c 36 x 0.3200.03 0.15 c m bottom view ab top view 0.025 a b 0.15 c m 3.0880.03 material & lead finish package material: epoxy resin, halogen (br and cl) free solder ball material: snagcu
[AK4955] ms1343-e-00 2011/12 - 116 - marking 4955 xxxx 1 xxxx: date code (4 digit) pin #1 indication date (yy/mm/dd) revision reason page contents 11/12/28 00 first edition revision history
[AK4955] ms1343-e-00 2011/12 - 117 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK4955

	To Download AK4955 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .